Strong correlation between dielectric reliability and charge trapping in SiO2 / Al2O3 gate stacks with TiN electrodes

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2002, Pages 76-77

  Kerber, Andreas ^a   Cartier, E ^a   Degraeve, R ^a   Pantisano, L ^a   Roussel, Ph ^a   Groeseneken, G ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL VAPOR DEPOSITION; CURRENT DENSITY; ELECTRIC CHARGE; ELECTRODES; ELECTRON TRAPS; INTERFACES (MATERIALS); MOS CAPACITORS; PHOTOLITHOGRAPHY; PHYSICAL VAPOR DEPOSITION; POLYSILICON; SILICON WAFERS;

CHARGE TRAPPING;

GATES (TRANSISTOR);

EID: 0036045181     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)