Novel techniques for reducing self-heating effects in silicon-on-insulator power devices

Proceedings of the International Semiconductor Conference, CAS

Volumn 2, Issue , 2001, Pages 493-496

  Roig, J ^a   Flores, D ^a   Vellvehi, M ^a   Rebollo, J ^a   Millan, J ^a  

^a INSTITUTO DE MICROELECTRÓNICA DE BARCELONA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC CURRENTS; ELECTRIC LOSSES; HIGH TEMPERATURE OPERATIONS; OXIDES; SEMICONDUCTING SILICON; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES; THERMAL CONDUCTIVITY;

BURIED OXIDE LAYER; ELECTRICAL ISOLATION; ELECTROTHERMAL; POWER DEVICES; POWER LOSSES; SELF HEATING EFFECTS; THERMAL ISOLATION;

SEMICONDUCTOR DEVICES;

EID: 0035744216     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. Intelligent power IC with partial SOI structure
2. Comparison of self-heating effects in bulk-silicon and SOI high-voltage devices
3. Thermal behaviour of lateral power devices on SOI substrates
4. Self-heating effect in lateral DMOS on SOI
5. High voltage silicon-on-insulator (SOI) MOSFETs
6. Lateral insulated gate bipolar transistor (LIGBT) structure based on partial isolation SOI technology
7. From SOI to SOIM technology: Application for specific semiconductor processes
8. Reduction on self-heating effect on SOIM devices
9. Device characteristics of a 30-V-Class thin-film SOI power MOSFET
10. Thermal and package performance limitations in LDMOSFET's for RFIC applications