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Volumn 20, Issue 6, 2005, Pages 652-657

Study of the extrinsic parasitics in nano-scale transistors

Author keywords

[No Author keywords available]

Indexed keywords

ARSENIC; CAPACITANCE; COMPUTER SIMULATION; CONCENTRATION (PROCESS); CONFORMAL MAPPING; DIELECTRIC MATERIALS; DOPING (ADDITIVES);

EID: 18744405688     PISSN: 02681242     EISSN: None     Source Type: Journal    
DOI: 10.1088/0268-1242/20/6/029     Document Type: Article
Times cited : (9)

References (15)
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  • 6
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    • Ideal rectangular cross-section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching
    • 10.1109/LED.2003.815004 0741-3106
    • Liu Y, Ishii K, Tsutsumi T, Masahara M and Suzuki E 2003 Ideal rectangular cross-section Si-Fin channel double-gate MOSFETs fabricated using orientation-dependent wet etching IEEE Electron Device Lett. 24 484-6
    • (2003) IEEE Electron Device Lett. , vol.24 , Issue.7 , pp. 484-486
    • Liu, Y.1    Ishii, K.2    Tsutsumi, T.3    Masahara, M.4    Suzuki, E.5
  • 8
    • 0347968246 scopus 로고    scopus 로고
    • Physically based modeling of low field electron mobility in ultrathin single- and double-gate SOI n-MOSFETs
    • 10.1109/TED.2003.819256 0018-9383
    • Esseni D, Abramo A, Selmi L and Sangiorgi E 2003 Physically based modeling of low field electron mobility in ultrathin single- and double-gate SOI n-MOSFETs IEEE Trans. Electron Devices 50 2445-55
    • (2003) IEEE Trans. Electron Devices , vol.50 , Issue.12 , pp. 2445-2455
    • Esseni, D.1    Abramo, A.2    Selmi, L.3    Sangiorgi, E.4
  • 9
    • 1342265609 scopus 로고    scopus 로고
    • On the electron mobility in ultrathin SOI and GOI
    • 10.1109/LED.2003.822650 0741-3106
    • Khakifirooz A and Antoniadis D A 2004 On the electron mobility in ultrathin SOI and GOI IEEE Electron Device Lett. 25 80-2
    • (2004) IEEE Electron Device Lett. , vol.25 , Issue.2 , pp. 80-82
    • Khakifirooz, A.1    Antoniadis, D.A.2
  • 10
    • 0037870335 scopus 로고    scopus 로고
    • An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode
    • 10.1109/TED.2002.807444 0018-9383
    • Esseni D, Mastrapasqua M, Celler G K, Fiegna C, Selmi L and Sangiorgi E 2003 An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode IEEE Trans. Electron Devices 50 802-8
    • (2003) IEEE Trans. Electron Devices , vol.50 , Issue.3 , pp. 802-808
    • Esseni, D.1    Mastrapasqua, M.2    Celler, G.K.3    Fiegna, C.4    Selmi, L.5    Sangiorgi, E.6
  • 11
    • 0001114294 scopus 로고    scopus 로고
    • Electronic structures and phonon limited electron mobility of double-gate silicon-on-insulator Si inversion layers
    • 10.1063/1.369589 0021-8979
    • Shoji M and Horiguchi S 1999 Electronic structures and phonon limited electron mobility of double-gate silicon-on-insulator Si inversion layers J. Appl. Phys. 85 2722-31
    • (1999) J. Appl. Phys. , vol.85 , Issue.5 , pp. 2722-2731
    • Shoji, M.1    Horiguchi, S.2
  • 12
    • 0000323067 scopus 로고    scopus 로고
    • Phonon-limited inversion layer electron mobility in extremely thin Si layer of silicon-on-insulator metal-oxide-semiconductor field-effect transistor
    • 10.1063/1.366480 0021-8979
    • Shoji M and Horiguchi S S 1997 Phonon-limited inversion layer electron mobility in extremely thin Si layer of silicon-on-insulator metal-oxide-semiconductor field-effect transistor J. Appl. Phys. 82 6096-101
    • (1997) J. Appl. Phys. , vol.82 , Issue.12 , pp. 6096-6101
    • Shoji, M.1    Horiguchi, S.S.2
  • 13
    • 0036927506 scopus 로고    scopus 로고
    • Experimental study on carrier transport mechanism in ultrathin-body SOI n- and p-MOSFETs with SOI thickness less than 5 nm
    • Uchida K, Watanabe H, Kinoshita A, Koga J, Numata T and Takagi S 2002 Experimental study on carrier transport mechanism in ultrathin-body SOI n- and p-MOSFETs with SOI thickness less than 5 nm IEDM Tech. Dig. 47-50
    • (2002) IEDM Tech. Dig. , pp. 47-50
    • Uchida, K.1    Watanabe, H.2    Kinoshita, A.3    Koga, J.4    Numata, T.5    Takagi, S.6
  • 14
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    • Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs
    • 10.1109/TNANO.2003.820780 1536-125X
    • Shenoy R S and Saraswat K C 2003 Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs IEEE Trans. Nanotechnol. 2 265-70
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    • Modeling the fringing electric field effect on the threshold voltage of FD SOI nMOS devices with the LDD/sidewall oxide spacer structure
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    • Lin S C and Kuo J B 2003 Modeling the fringing electric field effect on the threshold voltage of FD SOI nMOS devices with the LDD/sidewall oxide spacer structure IEEE Trans. Electron Devices 50 2559-64
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.