-
1
-
-
37149024045
-
Design patterns: Abstraction and reuse of object-oriented design
-
July
-
E. Gamma, R. Helm, R. Johnson, and J. Vlissides, "Design Patterns: Abstraction and Reuse of Object-Oriented Design," in Proceedings of the European Conference on Object-Oriented Programming (ECOOP), July 1993, pp. 406-431.
-
(1993)
Proceedings of the European Conference on Object-oriented Programming (ECOOP)
, pp. 406-431
-
-
Gamma, E.1
Helm, R.2
Johnson, R.3
Vlissides, J.4
-
4
-
-
84976676955
-
The paradigms of progamming
-
R. W. Floyd, "The Paradigms of Progamming," Communications of the ACM, vol. 22, no. 8, pp. 455-460, 1979.
-
(1979)
Communications of the ACM
, vol.22
, Issue.8
, pp. 455-460
-
-
Floyd, R.W.1
-
5
-
-
0029521029
-
Video communications using rapidly reconfigurable hardware
-
December
-
J. Villasenor, C. Jones, and B. Schoner, "Video Communications using Rapidly Reconfigurable Hardware," IEEE Transactions on Circuits and Systems for Video Technology, vol. 5, pp. 565-567, December 1995.
-
(1995)
IEEE Transactions on Circuits and Systems for Video Technology
, vol.5
, pp. 565-567
-
-
Villasenor, J.1
Jones, C.2
Schoner, B.3
-
6
-
-
0030415239
-
Configurable computer solutions for automatic target recognition
-
IEEE, April
-
J. Villasenor, B. Schoner, K.-N. Chia, and C. Zapata, "Configurable Computer Solutions for Automatic Target Recognition," in FCCM. IEEE, April 1996, pp. 70-79.
-
(1996)
FCCM.
, pp. 70-79
-
-
Villasenor, J.1
Schoner, B.2
Chia, K.-N.3
Zapata, C.4
-
7
-
-
0028737766
-
Density enhancement of a neural network using FPGAs and run-time reconfiguration
-
April
-
J. G. Eldredge and B. L. Hutchings, "Density Enhancement of a Neural Network Using FPGAs and Run-Time Reconfiguration," in FCCM, April 1994, pp. 180-188.
-
(1994)
FCCM
, pp. 180-188
-
-
Eldredge, J.G.1
Hutchings, B.L.2
-
8
-
-
0037581167
-
Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and tutorial
-
short version appears in
-
E. Caspi, M. Chu, R. Huang, N. Weaver, J. Yeh, J. Wawrzynek, and A. DeHon, "Stream Computations Organized for Reconfigurable Execution (SCORE): Introduction and Tutorial," 〈http://www.cs. berkeley.edu/projects/ brass/documents/score_tutorial.html〉, short version appears in FPL'2000 (LNCS 1896), 2000.
-
(2000)
FPL'2000 (LNCS)
, vol.1896
-
-
Caspi, E.1
Chu, M.2
Huang, R.3
Weaver, N.4
Yeh, J.5
Wawrzynek, J.6
Dehon, A.7
-
9
-
-
0036382746
-
Analysis of quasiStatic scheduling techniques in a virtualized reconfigurable machine
-
February
-
Y. Markovskiy, E. Caspi, R. Huang, J. Yeh, M. Chu, J. Wawrzynek, and A. DeHon, "Analysis of QuasiStatic Scheduling Techniques in a Virtualized Reconfigurable Machine," in FPGA, February 2002, pp. 196-205.
-
(2002)
FPGA
, pp. 196-205
-
-
Markovskiy, Y.1
Caspi, E.2
Huang, R.3
Yeh, J.4
Chu, M.5
Wawrzynek, J.6
Dehon, A.7
-
10
-
-
0033281039
-
Embedded DRAM for a reconfigurable array
-
June
-
S. Perissakis, Y. Joo, J. Ahn, A. DeHon, and J. Wawrzynek, "Embedded DRAM for a Reconfigurable Array," in Proceedings of the 1999 Symposium on VLSI Circuits, June 1999.
-
(1999)
Proceedings of the 1999 Symposium on VLSI Circuits
-
-
Perissakis, S.1
Joo, Y.2
Ahn, J.3
Dehon, A.4
Wawrzynek, J.5
-
11
-
-
0029490721
-
Design methodologies for partially reconfigured systems
-
April
-
J. D. Hadley and B. Hutchings, "Design Methodologies for Partially Reconfigured Systems," in FCCM, April 1995, pp. 78-84.
-
(1995)
FCCM
, pp. 78-84
-
-
Hadley, J.D.1
Hutchings, B.2
-
12
-
-
84963956653
-
Configuration compression for virtex FPGAs
-
Z. Li and S. Hauck, "Configuration Compression for Virtex FPGAs," in FCCM, 2001.
-
(2001)
FCCM
-
-
Li, Z.1
Hauck, S.2
-
13
-
-
0002799279
-
Fast integer multipliers fit in FPGAs
-
May 12
-
K. D. Chapman, "Fast Integer Multipliers fit in FPGAs," EDN, vol. 39, no. 10, p. 80, May 12 1993.
-
(1993)
EDN
, vol.39
, Issue.10
, pp. 80
-
-
Chapman, K.D.1
-
14
-
-
0003651029
-
-
Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124
-
The Programmable Logic Data Book, Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, 1993.
-
(1993)
The Programmable Logic Data Book
-
-
-
15
-
-
0003460244
-
-
Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, April dS003
-
Xilinx Virtex 2.5V Field Programmable Gate Arrays, Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, April 2001, dS003 〈http://direct.xilinx. com/bvdocs/publications/ds003.pdf〉.
-
(2001)
Xilinx Virtex 2.5V Field Programmable Gate Arrays
-
-
-
16
-
-
0029539752
-
Run time reconfiguration of FPGA for scanning genomic databases
-
April
-
E. Lemoine and D. Merceron, "Run Time Reconfiguration of FPGA for Scanning Genomic Databases," in FCCM, April 1995, pp. 90-98.
-
(1995)
FCCM
, pp. 90-98
-
-
Lemoine, E.1
Merceron, D.2
-
17
-
-
0037581172
-
-
Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, September xAPP 203
-
Designing Flexible, Fast CAMs with Virtex Family FPGAs, Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, September 1999, xAPP 203 〈http://www.xilinx.com/bvdocs/appnotes/xapp203.pdf〉.
-
(1999)
Designing Flexible, Fast CAMs with Virtex Family FPGAs
-
-
-
18
-
-
18644376121
-
-
Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, June
-
XC6200 FPGA Advanced Product Specification, Version 1.0 ed., Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, June 1996.
-
(1996)
XC6200 FPGA Advanced Product Specification, Version 1.0 Ed.
-
-
-
19
-
-
84860931673
-
-
Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, October 200 dS031
-
Xilinx Virtex-II Platform FPGAs Data Sheet, Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, October 2003, dS031 〈http://direct.xilinx.com/ bvdocs/publications/ds031.pdf〉.
-
(2003)
Xilinx Virtex-II Platform FPGAs Data Sheet
-
-
-
20
-
-
0034174174
-
The carp architecture and C compiler
-
April
-
T. Callahan, J. Hauser, and J. Wawrzynek, "The Carp Architecture and C Compiler," IEEE Computer, vol. 33, no. 4, pp. 62-69, April 2000.
-
(2000)
IEEE Computer
, vol.33
, Issue.4
, pp. 62-69
-
-
Callahan, T.1
Hauser, J.2
Wawrzynek, J.3
-
21
-
-
85027013675
-
Spyder: A reconfigurante VLIW Processor using FPGAs
-
April
-
C. Iseli and E. Sanchez, "Spyder: A Reconfigurante VLIW Processor using FPGAs," in FCCM, April 1993, pp. 17-24.
-
(1993)
FCCM
, pp. 17-24
-
-
Iseli, C.1
Sanchez, E.2
-
22
-
-
0029703253
-
DPGA utilization and application
-
February
-
A. DeHon, "DPGA Utilization and Application," in FPGA, February 1996, pp. 115-121.
-
(1996)
FPGA
, pp. 115-121
-
-
DeHon, A.1
-
23
-
-
0031645555
-
Managing pipeline-reconfigurable FPGAs
-
S. Cadambi, J. Weener, S. Goldstein, H. Schmit, and D. Thomas, "Managing pipeline-reconfigurable FPGAs," in FPGA, 1998, pp. 55-64.
-
(1998)
FPGA
, pp. 55-64
-
-
Cadambi, S.1
Weener, J.2
Goldstein, S.3
Schmit, H.4
Thomas, D.5
-
26
-
-
0028455029
-
On area/depth trade-off in LUT-based FPGA technology mapping
-
June
-
J. Cong and Y. Ding, "On Area/Depth Trade-Off in LUT-Based FPGA Technology Mapping," IEEE Transactions on VLSI Design, vol. 2, no. 2, pp. 137-148, June 1994.
-
(1994)
IEEE Transactions on VLSI Design
, vol.2
, Issue.2
, pp. 137-148
-
-
Cong, J.1
Ding, Y.2
-
29
-
-
0029181665
-
High-level bit-serial datapath synthesis for multi-FPGA systems
-
ACM, February
-
T. Isshiki and W. W.-M. Dai, "High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems," in FPGA. ACM, February 1995, pp. 167-173.
-
(1995)
FPGA
, pp. 167-173
-
-
Isshiki, T.1
Dai, W.W.-M.2
-
30
-
-
0141521394
-
A variable long-precision arithmetic unit designed for reconifgurable coprocessor architectures
-
A. F. Tenca and M. D. Ercegovac, "A Variable Long-Precision Arithmetic Unit Designed for Reconifgurable Coprocessor Architectures," in FCCM, 1998, pp. 216-225.
-
(1998)
FCCM
, pp. 216-225
-
-
Tenca, A.F.1
Ercegovac, M.D.2
-
31
-
-
0035242871
-
An automated process for compiling dataflow graphs into reconfigurable hardware
-
R. Rinker, M. Carter, A. Patel, M. Chawathe, C. Ross, J. Hammes, W. A. Najjar, and W. Böhm, "An Automated Process for Compiling Dataflow Graphs into Reconfigurable Hardware," IEEE Transactions on VLSI Systems, vol. 9, no. 1, pp. 130-139, 2001.
-
(2001)
IEEE Transactions on VLSI Systems
, vol.9
, Issue.1
, pp. 130-139
-
-
Rinker, R.1
Carter, M.2
Patel, A.3
Chawathe, M.4
Ross, C.5
Hammes, J.6
Najjar, W.A.7
Böhm, W.8
-
32
-
-
84939698077
-
Synchronous data flow
-
September
-
E. A. Lee and D. G. Messerschmitt, "Synchronous Data Flow," Proceedings of the IEEE, vol. 75, no. 9, pp. 1235-1245, September 1987.
-
(1987)
Proceedings of the IEEE
, vol.75
, Issue.9
, pp. 1235-1245
-
-
Lee, E.A.1
Messerschmitt, D.G.2
-
33
-
-
0022882379
-
Data parallel algorithms
-
December
-
W. D. Hillis and G. L. Steele, "Data Parallel Algorithms," Communications of the ACM, vol. 29, no. 12, pp. 1170-1183, December 1986.
-
(1986)
Communications of the ACM
, vol.29
, Issue.12
, pp. 1170-1183
-
-
Hillis, W.D.1
Steele, G.L.2
-
34
-
-
84955573032
-
FPGA computing in a data parallel C
-
April
-
M. Gokhale and R. Minnich, "FPGA Computing in a Data Parallel C," in FCCM, April 1993, pp. 94-101.
-
(1993)
FCCM
, pp. 94-101
-
-
Gokhale, M.1
Minnich, R.2
-
35
-
-
18644365549
-
A data-parallel programming model for reconfigurable architectures
-
April
-
S. Guccione and M. Gonzalez, "A Data-Parallel Programming Model for Reconfigurable Architectures," in FCCM, April 1993, pp. 79-87.
-
(1993)
FCCM
, pp. 79-87
-
-
Guccione, S.1
Gonzalez, M.2
-
38
-
-
84976721284
-
Multilisp: A language for concurrent symbolic computation
-
R. H. Halstead, Jr., "Multilisp: A Language for Concurrent Symbolic Computation," ACM Transaction on Programming Languages and Systems, vol. 7, no. 4, pp. 501-538, 1985.
-
(1985)
ACM Transaction on Programming Languages and Systems
, vol.7
, Issue.4
, pp. 501-538
-
-
Halstead Jr., R.H.1
-
39
-
-
0003707211
-
-
10662 Los Vasqueros Circle, PO Box 3014, Los Alamitos, CA 90720-1264: IEEE Computer Society Press
-
D. Buell, J. Arnold, and W. Kleinfelder, Splash 2: FPGAs in a Custom Computing Machine. 10662 Los Vasqueros Circle, PO Box 3014, Los Alamitos, CA 90720-1264: IEEE Computer Society Press, 1996.
-
(1996)
Splash 2: FPGAs in a Custom Computing Machine
-
-
Buell, D.1
Arnold, J.2
Kleinfelder, W.3
-
40
-
-
0032627649
-
Memory interfacing and instruction specification for reconfigurable processors
-
February
-
J. A. Jacob and P. Chow, "Memory Interfacing and Instruction Specification for Reconfigurable Processors," in FPGA, February 1999, pp. 145-154.
-
(1999)
FPGA
, pp. 145-154
-
-
Jacob, J.A.1
Chow, P.2
-
41
-
-
0033488527
-
Pipeline vectorization for reconfigurable systems
-
M. Weinhardt and W. Luk, "Pipeline Vectorization for Reconfigurable Systems," in FCCM, 1999, pp. 52-62.
-
(1999)
FCCM
, pp. 52-62
-
-
Weinhardt, M.1
Luk, W.2
-
43
-
-
0003379767
-
Accelerating boolean satisfiability with configurable hardware
-
April
-
P. Zhong, M. Martonosi, P. Ashar, and S. Malik, "Accelerating Boolean Satisfiability with Configurable Hardware," in FCCM, April 1998, pp. 186-195.
-
(1998)
FCCM
, pp. 186-195
-
-
Zhong, P.1
Martonosi, M.2
Ashar, P.3
Malik, S.4
-
44
-
-
0030364067
-
Solving graph problems with dynamic computational structures
-
November
-
J. Babb, M. Frank, and A. Agarwal, "Solving Graph Problems with Dynamic Computational Structures," in Proceedings of SPIE: High-Speed Computing, Digital Signal Processing, and Filtering Using reconfigurable Logic, vol. 2914, November 1996, pp. 225-236.
-
(1996)
Proceedings of SPIE: High-speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic
, vol.2914
, pp. 225-236
-
-
Babb, J.1
Frank, M.2
Agarwal, A.3
-
45
-
-
0031344874
-
Fault simulation on reconfigurable hardware
-
April
-
M. Abramovici and P. Menon, "Fault Simulation on Reconfigurable Hardware," in FCCM, April 1997, pp. 182-190.
-
(1997)
FCCM
, pp. 182-190
-
-
Abramovici, M.1
Menon, P.2
-
46
-
-
0029514257
-
Flexible image acquisition using reconfigurable hardware
-
M. Shand, "Flexible Image Acquisition using Reconfigurable Hardware," in FCCM, 1995, pp. 125-134.
-
(1995)
FCCM
, pp. 125-134
-
-
Shand, M.1
-
47
-
-
0003168162
-
The NAPA adaptive processing architecture
-
April
-
C. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt, J. Arnold, and M. Gokhale, "The NAPA Adaptive Processing Architecture," in FCCM, April 1998, pp. 28-37.
-
(1998)
FCCM
, pp. 28-37
-
-
Rupp, C.1
Landguth, M.2
Garverick, T.3
Gomersall, E.4
Holt, H.5
Arnold, J.6
Gokhale, M.7
-
48
-
-
0031360911
-
Garp: A MIPS processor with a reconfigurable coprocessor
-
IEEE, April
-
J. R. Hauser and J. Wawrzynek, "Garp: A MIPS Processor with a Reconfigurable Coprocessor," in FCCM. IEEE, April 1997, pp. 12-21.
-
(1997)
FCCM
, pp. 12-21
-
-
Hauser, J.R.1
Wawrzynek, J.2
-
49
-
-
0027561268
-
Processor reconfiguration through instruction-set metamorphosis
-
March
-
P. Athanas and H. F. Silverman, "Processor Reconfiguration Through Instruction-Set Metamorphosis," IEEE Computer, vol. 26, no. 3, pp. 11-18, March 1993.
-
(1993)
IEEE Computer
, vol.26
, Issue.3
, pp. 11-18
-
-
Athanas, P.1
Silverman, H.F.2
-
51
-
-
0029545190
-
A dynamic instruction set computer
-
April
-
M. J. Wirthlin and B. L. Hutchings, "A Dynamic Instruction Set Computer," in FCCM, April 1995.
-
(1995)
FCCM
-
-
Wirthlin, M.J.1
Hutchings, B.L.2
-
52
-
-
0031362697
-
Compilation tools for run-time reconfigurable designs
-
April
-
W. Luk, N. Shirazi, and P. Y. K. Cheung, "Compilation Tools for Run-Time Reconfigurable Designs," in FCCM, April 1997, pp. 56-65.
-
(1997)
FCCM
, pp. 56-65
-
-
Luk, W.1
Shirazi, N.2
Cheung, P.Y.K.3
-
53
-
-
0031376640
-
The chimaera reconfigurable functional unit
-
April
-
S. Hauck, T. Fry, M. Hosler, and J. Kao, "The Chimaera Reconfigurable Functional Unit," in FCCM, April 1997, pp. 87-96.
-
(1997)
FCCM
, pp. 87-96
-
-
Hauck, S.1
Fry, T.2
Hosler, M.3
Kao, J.4
-
54
-
-
0033321638
-
DIVA: A reliable substrate for deep submicron microarchitecture design
-
T. M. Austin, "DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design," in MICRO, 1999, pp. 196-207.
-
(1999)
MICRO
, pp. 196-207
-
-
Austin, T.M.1
-
55
-
-
0029725182
-
The wave pipeline effect on LUT-based FPGA architectures
-
February
-
E. Boemo, S. López-Buedo, and J. M. Meneses, "The Wave Pipeline Effect on LUT-based FPGA Architectures," in FPGA, February 1996, pp. 45-50.
-
(1996)
FPGA
, pp. 45-50
-
-
Boemo, E.1
López-Buedo, S.2
Meneses, J.M.3
-
57
-
-
0032655186
-
HSRA: High-speed, hierarchical synchronous reconfigurable array
-
February
-
W. Tsu, K. Macy, A. Joshi, R. Huang, N. Walker, T. Tung, O. Rowhani, V. George, J. Wawrzynek, and A. DeHon, "HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array," in FPGA, February 1999, pp. 125-134.
-
(1999)
FPGA
, pp. 125-134
-
-
Tsu, W.1
Macy, K.2
Joshi, A.3
Huang, R.4
Walker, N.5
Tung, T.6
Rowhani, O.7
George, V.8
Wawrzynek, J.9
DeHon, A.10
-
58
-
-
0035007999
-
The case for registered routing switches in field-programmable gate arrays
-
February
-
D. P. Singh and S. D. Brown, "The Case for Registered Routing Switches in Field-Programmable Gate Arrays," in FPGA, February 2001, pp. 161-169.
-
(2001)
FPGA
, pp. 161-169
-
-
Singh, D.P.1
Brown, S.D.2
-
59
-
-
0038349119
-
Post-placement C-slow retiming for the xilinx virtex FPGA
-
N. Weaver, Y. Markovskiy, Y. Patel, and J. Wawrzynek, "Post-Placement C-slow Retiming for the Xilinx Virtex FPGA," in FPGA, 2003, pp. 185-194.
-
(2003)
FPGA
, pp. 185-194
-
-
Weaver, N.1
Markovskiy, Y.2
Patel, Y.3
Wawrzynek, J.4
-
60
-
-
84976725287
-
Software pipelining
-
September
-
V. H. Allan, R. B. Jones, R. M. Lee, and S. J. Allan, "Software Pipelining," ACM Computing Surveys, vol. 27, no. 3, pp. 367-432, September 1995.
-
(1995)
ACM Computing Surveys
, vol.27
, Issue.3
, pp. 367-432
-
-
Allan, V.H.1
Jones, R.B.2
Lee, R.M.3
Allan, S.J.4
-
62
-
-
0036385678
-
Performance-constrained pipelining of software loops onto reconfigurable hardware
-
G. Snider, "Performance-Constrained Pipelining of Software Loops onto Reconfigurable Hardware," in FPGA, 2003, pp. 177-186.
-
(2003)
FPGA
, pp. 177-186
-
-
Snider, G.1
-
63
-
-
0034174025
-
The density advantage of configurable computing
-
April
-
A. DeHon, "The Density Advantage of Configurable Computing," IEEE Computer, vol. 33, no. 4, pp. 41-49, April 2000.
-
(2000)
IEEE Computer
, vol.33
, Issue.4
, pp. 41-49
-
-
DeHon, A.1
-
64
-
-
0031340032
-
High level compilation for fine grained FPGAs
-
April
-
M. Gokhale and E. Gomersall, "High Level Compilation for Fine Grained FPGAs," in FCCM, April 1997, pp. 165-173.
-
(1997)
FCCM
, pp. 165-173
-
-
Gokhale, M.1
Gomersall, E.2
-
65
-
-
84956867255
-
Object oriented circuit-generators in java
-
April
-
M. Chu, N. Weaver, K. Sulimma, A. DeHon, and J. Wawrzynek, "Object Oriented Circuit-Generators in Java," in FCCM, April 1998, pp. 158-166.
-
(1998)
FCCM
, pp. 158-166
-
-
Chu, M.1
Weaver, N.2
Sulimma, K.3
Dehon, A.4
Wawrzynek, J.5
-
66
-
-
0030388817
-
Expressing dynamic reconfiguration by partial evaluation
-
April
-
S. Singh, J. Hogg, and D. McAuley, "Expressing Dynamic Reconfiguration by Partial Evaluation," in FCCM, April 1996, pp. 188-194.
-
(1996)
FCCM
, pp. 188-194
-
-
Singh, S.1
Hogg, J.2
McAuley, D.3
-
67
-
-
0031360912
-
Automated field-programmable compute accelerator design using partial evaluation
-
April
-
Q. Wang and D. M. Lewis, "Automated Field-Programmable Compute Accelerator Design Using Partial Evaluation," in FCCM, April 1997, pp. 145-154.
-
(1997)
FCCM
, pp. 145-154
-
-
Wang, Q.1
Lewis, D.M.2
-
69
-
-
0031374838
-
The swapable logic unit: A paradigm for virtual hardware
-
April
-
G. Brebner, "The Swapable Logic Unit: a Paradigm for Virtual Hardware," in FCCM, April 1997, pp. 77-86.
-
(1997)
FCCM
, pp. 77-86
-
-
Brebner, G.1
-
70
-
-
1642335516
-
-
Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, May xAPP 290
-
D. Lim and M. Peattie, Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations, Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, May 2002, xAPP 290 〈http://www.xilinx.com/bvdocs/appnotes/xapp290. pdf〉.
-
(2002)
Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations
-
-
Lim, D.1
Peattie, M.2
-
71
-
-
0029290549
-
Cheops: A reconfigurable data-flow system for video processing
-
April
-
V. M. Bove, Jr. and J. A. Watlington, "Cheops: A Reconfigurable Data-Flow System for Video Processing," IEEE Transactions on Circuits and Systems for Video Technology, vol. 5, no. 2, pp. 140-149, April 1995.
-
(1995)
IEEE Transactions on Circuits and Systems for Video Technology
, vol.5
, Issue.2
, pp. 140-149
-
-
Bove Jr., V.M.1
Watlington, J.A.2
-
72
-
-
0021793126
-
The cosmic cube
-
January
-
C. L. Seitz, "The Cosmic Cube," CACM, pp. 22-33, January 1985.
-
(1985)
CACM
, pp. 22-33
-
-
Seitz, C.L.1
-
73
-
-
0026867086
-
Active messages: A mechanism for integrated communication and computation
-
Queensland, Australia, May
-
T. v. Eicken et al., "Active Messages: a Mechanism for Integrated Communication and Computation," in Proceedings of the 19th Annual Symposium on Computer Architecture, Queensland, Australia, May 1992.
-
(1992)
Proceedings of the 19th Annual Symposium on Computer Architecture
-
-
Eicken, T.V.1
-
75
-
-
18644365942
-
Implementing an API for distributed adaptive computing systems
-
M. Jones, L. Scharf, J. Scott, C. Twaddle, M. Yaconis, K. Yao, P. Athanas, and B. Schott, "Implementing an API for Distributed Adaptive Computing Systems," in FCCM, 2001.
-
(2001)
FCCM
-
-
Jones, M.1
Scharf, L.2
Scott, J.3
Twaddle, C.4
Yaconis, M.5
Yao, K.6
Athanas, P.7
Schott, B.8
-
76
-
-
0040342812
-
-
Xerox Palo Alto Research Center, CSL 81-9
-
B. J. Nelson, "Remote Procedure Call," Xerox Palo Alto Research Center, CSL 81-9, 1981.
-
(1981)
Remote Procedure Call
-
-
Nelson, B.J.1
-
77
-
-
12344269990
-
Peer-to-peer hardware-software interfaces for reconfigurable fabrics
-
M. Budiu, M. Mishra, A. Bharambe, and S. C. Goldstein, "Peer-to-Peer Hardware-Software Interfaces for Reconfigurable Fabrics," in FCCM, 2002.
-
(2002)
FCCM
-
-
Budiu, M.1
Mishra, M.2
Bharambe, A.3
Goldstein, S.C.4
-
80
-
-
79955160157
-
Compiling application-specific hardware
-
M. Budiu and S. C. Goldstein, "Compiling Application-Specific Hardware," in FPL, 2002, pp. 853-863.
-
(2002)
FPL
, pp. 853-863
-
-
Budiu, M.1
Goldstein, S.C.2
-
83
-
-
0003260777
-
Transmission control protocol - DARPA internet program protocol specification
-
USC/ISI, Information Sciences Institute, University of Southern California, 4676 Admiralty Way, Marina del Rey, California, 90291, September
-
E. J. Postel, "Transmission Control Protocol - DARPA Internet Program Protocol Specification," USC/ISI, Information Sciences Institute, University of Southern California, 4676 Admiralty Way, Marina del Rey, California, 90291, RFC 793, September 1981.
-
(1981)
RFC
, vol.793
-
-
Postel, E.J.1
-
85
-
-
0000870032
-
The fantastic combinations of John conway's new solitaire game "life"
-
October
-
M. Gardner, "The Fantastic Combinations of John Conway's New Solitaire Game "life"," Scientific American, vol. 223, pp. 120-123, October 1970.
-
(1970)
Scientific American
, vol.223
, pp. 120-123
-
-
Gardner, M.1
-
86
-
-
85052713954
-
Realising massively concurrent systems on the SPACE machine
-
April
-
G. Milne, P. Cockshott, G. McCaskill, and P. Barrie, "Realising Massively Concurrent Systems on the SPACE Machine," in FCCM, April 1993, pp. 26-32.
-
(1993)
FCCM
, pp. 26-32
-
-
Milne, G.1
Cockshott, P.2
McCaskill, G.3
Barrie, P.4
-
87
-
-
0019923189
-
Why systolic architectures?
-
January
-
H. T. Rung, "Why Systolic Architectures?" IEEE Computer, vol. 15, no. 1, pp. 37-46, January 1982.
-
(1982)
IEEE Computer
, vol.15
, Issue.1
, pp. 37-46
-
-
Rung, H.T.1
-
88
-
-
0030671953
-
Signal processing at 250 MHz using high-performance FPGA's
-
February
-
B. V. Herzen, "Signal Processing at 250 MHz using High-Performance FPGA's," in FPGA, February 1997, pp. 62-68.
-
(1997)
FPGA
, pp. 62-68
-
-
Herzen, B.V.1
-
89
-
-
0022920181
-
-
ser. Distributed Computing. Springer-Verlag
-
W. J. Dally and C. L. Sietz, The Torus Routing Chip, ser. Distributed Computing. Springer-Verlag, 1986, vol. 1, pp. 187-196.
-
(1986)
The Torus Routing Chip
, vol.1
, pp. 187-196
-
-
Dally, W.J.1
Sietz, C.L.2
-
90
-
-
0021412333
-
A framework for solving VLSI graph layout problems
-
S. Bhatt and F. T. Leighton, "A Framework for Solving VLSI Graph Layout Problems," Journal of Computer System Sciences, vol. 28, pp. 300-343, 1984.
-
(1984)
Journal of Computer System Sciences
, vol.28
, pp. 300-343
-
-
Bhatt, S.1
Leighton, F.T.2
-
91
-
-
38249032515
-
A compact layout for the three-dimensional tree of meshes
-
R. I. Greenberg and C. E. Leiserson, "A Compact Layout for the Three-Dimensional Tree of Meshes," Applied Math Letters, vol. 1, no. 2, pp. 171-176, 1988.
-
(1988)
Applied Math Letters
, vol.1
, Issue.2
, pp. 171-176
-
-
Greenberg, R.I.1
Leiserson, C.E.2
-
92
-
-
33645263506
-
-
Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, December uG035
-
RocketIO X Transceiver User Guide, Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, December 2002, uG035 〈http://www.xilinx.com/bvdocs/ userguides/ug035.pdf〉.
-
(2002)
RocketIO X Transceiver User Guide
-
-
-
93
-
-
85027124029
-
Virtual wires: Overcoming pin limitations in FPGA-based logic emulators
-
April
-
J. Babb, R. Tessier, and A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators," in FCCM, April 1993, pp. 142-151.
-
(1993)
FCCM
, pp. 142-151
-
-
Babb, J.1
Tessier, R.2
Agarwal, A.3
-
94
-
-
0028292899
-
METRO: A router architecture for high-performance, short-haul routing networks
-
May
-
A. DeHon, F. Chong, M. Becker, E. Egozy, H. Minsky, S. Peretz, and T. F. Knight, Jr., "METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks," in ISCA, May 1994, pp. 266-277.
-
(1994)
ISCA
, pp. 266-277
-
-
Dehon, A.1
Chong, F.2
Becker, M.3
Egozy, E.4
Minsky, H.5
Peretz, S.6
Knight Jr., T.F.7
-
95
-
-
0034848112
-
Route packets, not wires: On-chip interconnection networks
-
W. J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," in Design Automation Conference, 2001, pp. 684-689.
-
(2001)
Design Automation Conference
, pp. 684-689
-
-
Dally, W.J.1
Towles, B.2
-
96
-
-
0032680472
-
Media processing with field-programmable gate arrays on a microprocessor's local bus
-
V. M. Bove, Jr., M. Lee, C. McEniry, T. Nwodoh, and J. Watlington, "Media Processing with Field-Programmable Gate Arrays on a Microprocessor's Local Bus," in Proceedings of SPIE Media Processors, vol. 3655, 1999.
-
(1999)
Proceedings of SPIE Media Processors
, vol.3655
-
-
Bove Jr., V.M.1
Lee, M.2
McEniry, C.3
Nwodoh, T.4
Watlington, J.5
-
97
-
-
51949110623
-
A reconfigurable content addressable memory
-
S. A. Guccione, D. Levi, and D. Downs, "A Reconfigurable Content Addressable Memory," in Proceedings of the International Parallel and Distributed Processing Symposium, 2000, pp. 882-889.
-
(2000)
Proceedings of the International Parallel and Distributed Processing Symposium
, pp. 882-889
-
-
Guccione, S.A.1
Levi, D.2
Downs, D.3
-
98
-
-
84995478726
-
FBRAM: A new form of memory optimized for 3D graphics
-
M. F. Deering, S. A. Schlapp, and M. G. Lavelle, "FBRAM: A new Form of Memory Optimized for 3D Graphics," in Proceedings of SIGGRAPH, 1994, pp. 167-174.
-
(1994)
Proceedings of SIGGRAPH
, pp. 167-174
-
-
Deering, M.F.1
Schlapp, S.A.2
Lavelle, M.G.3
-
99
-
-
0022216543
-
Architecture of the symbolics 3600
-
D. A. Moon, "Architecture of the Symbolics 3600," in ISCA, 1985, pp. 76-83.
-
(1985)
ISCA
, pp. 76-83
-
-
Moon, D.A.1
-
100
-
-
84942855387
-
Data search and reorganization using FPGAs: Application to spatial pointer-based data structures
-
P. Diniz and J. Park, "Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures," in FCCM, 2003, pp. 207-217.
-
(2003)
FCCM
, pp. 207-217
-
-
Diniz, P.1
Park, J.2
-
101
-
-
18644363619
-
Active Pages: A model of computation for intelligent memory
-
June
-
M. Oskin, F. T. Chong, and T. Sherwood, "Active Pages: a Model of Computation for Intelligent Memory," in ISCA, June 1998.
-
(1998)
ISCA
-
-
Oskin, M.1
Chong, F.T.2
Sherwood, T.3
-
102
-
-
0002546979
-
The compression cache: Using on-line compression to extend physical memory
-
F. Douglis, "The Compression Cache: Using On-line Compression to Extend Physical Memory," in Proceedings of the Winter USENIX Conference, 1993, pp. 519-529.
-
(1993)
Proceedings of the Winter USENIX Conference
, pp. 519-529
-
-
Douglis, F.1
-
103
-
-
85084162609
-
The case for compressed caching in virtual memory systems
-
P. R. Wilson, S. F. Kaplan, and Y. Smaragdakis, "The Case for Compressed Caching in Virtual Memory Systems," in Proceedings of the Summer USENIX Conference, 1999, pp. 101-116.
-
(1999)
Proceedings of the Summer USENIX Conference
, pp. 101-116
-
-
Wilson, P.R.1
Kaplan, S.F.2
Smaragdakis, Y.3
-
104
-
-
18644366213
-
-
Carnegie-Mellon University, Pittsbugh, Pennsylvania 15213, CMU-CS-TR 115, April
-
C. Leiserson, "Systolic Priority Queues," Carnegie-Mellon University, Pittsbugh, Pennsylvania 15213, CMU-CS-TR 115, April 1979.
-
(1979)
Systolic Priority Queues
-
-
Leiserson, C.1
-
105
-
-
23044533725
-
HAGAR: Efficient multicontext graph processors
-
O. Mencer, Z. Huang, and L. Huelsbergen, "HAGAR: Efficient Multicontext Graph Processors," in FPL, 2002, pp. 915-924.
-
(2002)
FPL
, pp. 915-924
-
-
Mencer, O.1
Huang, Z.2
Huelsbergen, L.3
-
106
-
-
84942932890
-
Floating point unit generation and evaluation for FPGAs
-
J. Liang, R. Tessier, and O. Mencer, "Floating Point Unit Generation and Evaluation for FPGAs," in FCCM, 2003, pp. 185-194.
-
(2003)
FCCM
, pp. 185-194
-
-
Liang, J.1
Tessier, R.2
Mencer, O.3
-
107
-
-
79955132452
-
Logarithmic number system and floating point arithmetics on FPGA
-
R. Matoušek, M. Tichý, Z. Pohl, J. Kadlec, C. Softley, and N. Coleman, "Logarithmic Number System and Floating Point Arithmetics on FPGA," in FPL, 2002, pp. 627-636.
-
(2002)
FPL
, pp. 627-636
-
-
Matoušek, R.1
Tichý, M.2
Pohl, Z.3
Kadlec, J.4
Softley, C.5
Coleman, N.6
-
108
-
-
0036384127
-
Parallel-beam backprojection: An FPGA implemenation optimzied for medical imaging
-
S. Coric, M. Lesser, E. Miller, and M. Trepanier, "Parallel-Beam Backprojection: An FPGA Implemenation Optimzied for Medical Imaging," in FPGA, 2003, pp. 217-226.
-
(2003)
FPGA
, pp. 217-226
-
-
Coric, S.1
Lesser, M.2
Miller, E.3
Trepanier, M.4
-
110
-
-
0031368023
-
Implementation of single precision floating point square root on FPGAs
-
Y. Li and W. Chu, "Implementation of Single Precision Floating Point Square Root on FPGAs," in FCCM, 1997, pp. 226-232.
-
(1997)
FCCM
, pp. 226-232
-
-
Li, Y.1
Chu, W.2
-
111
-
-
0027640821
-
FIR filters with field-programmable gate arrays
-
L. Mintzer, "FIR Filters with Field-Programmable Gate Arrays," Journal of VLSI Signal Processing, vol. 6, pp. 119-127, 1993.
-
(1993)
Journal of VLSI Signal Processing
, vol.6
, pp. 119-127
-
-
Mintzer, L.1
-
112
-
-
84873871151
-
A stochastic neural architecture that exploits dynamically reconfigurable FPGAs
-
April
-
M. van Daalen, P. Jeavons, and J. Shawe-Taylor, "A Stochastic Neural Architecture that Exploits Dynamically Reconfigurable FPGAs," in FCCM, April 1993, pp. 202-211.
-
(1993)
FCCM
, pp. 202-211
-
-
Van Daalen, M.1
Jeavons, P.2
Shawe-Taylor, J.3
-
113
-
-
0029713021
-
Structure design and implemenation - A strategy for implementing regular datapaths on FPGAs
-
February
-
A. Koch, "Structure Design and Implemenation - A Strategy for Implementing Regular Datapaths on FPGAs," in FPGA, February 1996, pp. 151-157.
-
(1996)
FPGA
, pp. 151-157
-
-
Koch, A.1
|