Configuration Compression for Virtex FPGAs

Proceedings - 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2001

Volumn , Issue , 2001, Pages 147-159

  Li, Zhiyuan ^a   Hauck, S ^b  

^a Northwestern University   (United States)

^b University of Washington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); COMPUTER HARDWARE; COMPUTERS; DATA COMPRESSION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE;

COMPRESSION TECHNIQUES; CONFIGURATION BITSTREAM; HARDWARE AND SOFTWARE; HARDWARE STRUCTURES; MICROPROCESSOR SYSTEMS; PARTIAL RECONFIGURATION; RECONFIGURABLE SYSTEMS; RUN-TIME RECONFIGURABLE SYSTEMS;

RECONFIGURABLE HARDWARE;

EID: 84963956653     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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