Compilation tools for run-time reconfigurable designs

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn , Issue , 1997, Pages 56-65

  Luk, Wayne ^a   Shirazi, Nabeel ^a   Cheung, Peter Y K ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER PROGRAMMING LANGUAGES; LOGIC CIRCUITS; LOGIC DESIGN; RESPONSE TIME (COMPUTER SYSTEMS);

COMPILE TIME SEQUENCING PROCESS; FIELD PROGRAMMABLE GATE ARRAY; INCREMENTAL CONFIGURATION CALCULATOR; PARTIAL EVALUATOR; RUN TIME RECONFIGURATION;

COMPUTER AIDED SOFTWARE ENGINEERING;

EID: 0031362697     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)