Data search and reorganization using FPGAs: Application to spatial pointer-based data structures

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2003-January, Issue , 2003, Pages 207-217

  Diniz, P C ^a   Park, Joonseok ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

Bandwidth; Computer architecture; Data structures; Field programmable gate arrays; Hardware; Logic circuits; Parallel processing; Permission; Reconfigurable logic; Search engines

Indexed keywords

BANDWIDTH; COMPUTATION THEORY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTERS; DATA STRUCTURES; LOGIC CIRCUITS; LOGIC GATES; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE; SEARCH ENGINES;

DATA REORGANIZATION; DATA SEARCHES; FINE GRAIN PARALLELISM; PARALLEL PROCESSING; PERMISSION; POINTER-BASED DATA STRUCTURES; RECONFIGURABLE LOGIC; RECONFIGURABLE TECHNOLOGIES;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84942855387     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2003.1227256     Document Type: Conference Paper

References (20)

1. F. Balasa, F. Catthoor, and H. De Man "Dataflow-driven Memory Allocation for Multi-dimensional Signal Processing Systems", Proceedings of the IEEE International Conference on Computer Aided Design (ICCAD'94), Nov. 1994, pp. 31-34.
2. K. Cain, J. LeBak and A. Skjellum, "Data Reorganization and Future Embedded HPC Middleware", In Proc. of the Fourth Annual High-Performance Embedded Computing Workshop (HPEC'2000) Workshop, M.I.T. Lincoln Labs, Mass. 2000.
3. F. Catthoor, F. Franssen, S. Wuytack, L. Nachtergaele, and H. DeMan "Global communication and memory optimizing transformations for low power signal processing systems", IEEE workshop on VLSI signal processing, La Jolla, Calif., Oct. 1994.
4. P. Diniz and J. Park, "Data Reorganization Engines for the Next Generation of FPGAs", In Proc. of the ACM Conf. on Field-Programmable-Gate-Arrays (FPGA'02), Feb. 2002 pp. 100-110.
5. M. Gokhale and J. Stone "Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks", In Proc. of IEEE Symp. on FPGAs for Custom Computing Machines (FCCM'99), IEEE Computer Society Press, 1999.
6. M. Hall, et. al., "Mapping Irregular Applications to DIVA, A PIM-based Data-Intensive Architecture" In Proc. of the Supercomputing Conference (SC'99), November 1999.
7. Y. Kang, et. al., "FlexRAM: Towards and Advanced Intelligent Memory System", In Proc. of the Intl. Conf. on Computer Design (ICCAD'99), IEEE Computer Society Press, pp. 192-201, 1999.
8. M. Miranda, F.Catthoor, M. Janssen and H. DeMan, "High-level address optimization and synthesis techniques for data-transfer-intensive applications", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6(4), Dec. 1998, pp. 677-686.
9. M. Oskin, F. Chong and T. Sherwood, "Active Pages: A Computational Model for Intelligent Memory", In Proc. of the Intl. Symp. On Computer Architectures (ISCA'98), pp. 192-203, 1998.
10. P. Panda, et. al. "Data and memory optimization techniques for embedded systems", ACM Transactions on Design Automation of Electronic System, 6(2), ACM Press, Apr. 2001, pp. 149-206.
11. J. Park and P. Diniz, "Synthesis of Memory Access Controllers for Streamed Data Applications for FPGA-based Computing Engines", In Proc. of the Intl Symp. on Systems Synthesis (ISSS'2001), IEEE Computer Society Press, Oct. 2001.
12. G. Rivera and C.-W. Tseng, "Data Transformations for Eliminating Cache Misses", In Proc. of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI'98), ACM Press, June 1998, pp. 38-49.
13. L. Séméria, K. Sato, G. De Micheli, "Synthesis of Hardware Models in C with Pointers and Complex Data Structures," In IEEE Transactions on VLSI, pp. 743-756, 9(6), Dec. 2001.
14. J. Setubal and J. Meidanis, "Introduction to Computational Molecular Biology", PWS Pub. Company, Boston, MA, 1997.
15. Synplify synthesis reference manual. Synplicity Inc, 2000.
16. WildStar™ Ref. Manual, Annapolis MicroSystems Inc., 1999.
17. J. Jean, G. Dong, H. Zhang, X. Guo, B. Zhang., "Query processing with an FPGA Coprocessor Board". In Proc. of The 1st Intl. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2001, Las Vegas, Nevada, USA.
18. XILINX, Inc. Virtex™ 2.5V Filed Programmable Gate Arrays Product Specification. DS003(v2.4), 2000.
19. nd Annual ACM Multimedia Conference, San Francisco, Ca., Oct., 1994.
20. P.H.W. Leong et al, "Pilchard - A Reconfigurable Computing Platform with Memory Slot Interface", In Proc. of IEEE Symp. on FPGAs for Custom Computing Machines (FCCM'01), Oct. 2001.