Post-placement C-slow retiming for the xilinx virtex FPGA

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2003, Pages 185-194

  Weaver, Nicholas ^a   Markovskiy, Yury ^a   Patel, Yatish ^a   Wawrzynek, John ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

C slow retiming; FPGA CAD; FPGA optimization; Retiming

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; CRYPTOGRAPHY; LOGIC DESIGN; POLYNOMIALS; SEMANTICS; SHIFT REGISTERS; THROUGHPUT;

C-SLOW RETIMING; SEQUENCE MATCHING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0038349119     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/611817.611845     Document Type: Conference Paper

References (18)

1. R. Alverson, D. Callahan, D. Cummings, B. Koblenz, A. Porterfield, and B. Smith. The tera computer system. In Proceedings of the ACM International Conference on Supercomputing, June 1990.
2. J. Cong and C. Wu. An improved algorithm for performance optimal technology mapping with retiming in LUT-based FPGA design. pages 572-578.
3. J. Cong and C. Wu. Optimal FPGA mapping and retiming with efficient initial state computation. In Design Automation Conference, pages 330-335, 1998.
4. J. Gaisler. Leon sparc-compatable processor.
5. Intel. Intel hyper-threading technology. 2001. http://developer.intel.com/technology/hyperthread/.
6. J. Laudon, A. Gupta, and M. Horowitz. Interleaving: A multithreading technique targeting multiprocessors and workstations. In Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 308-318, 1994.
7. C. Leiserson, F. Rose, and J. Saxe. Optimizing synchronous circuitry by retiming. In Third Caltech Conference On VLSI, March 1993.
8. NIST. Federal information processing standards publication 197: Advanced encryption standard, 2001. http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf.
9. NIST. Recommendations for block cypher modes of operation, nist special publication 800-38a, 2001. http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf.
10. D. P. Singh and S. D. Brown, Integrated retiming and placement for field programmable gate arrays. In Proceedings of the Tenth ACM International Symposium on Field Programmable Gate Arrays, 2002.
11. B. J. Smith. Architecture and application of the hep multiprocessor computer system. In SPIE, 298:241-248, 1981.
12. T. Smith and M. Waterman. Identification of common molecular subsequences, 1981.
13. Synopsys. Synopsys fpga compiler.
14. Synplify. Synplify fpga synthesis solution.
15. W. Tsu, K. Macy, A. Joshi, R. Huang, N. Walker, T. Tung, O. Rowhani, V. George, J. Wawrzynek, and A. DeHon. HSRA: High-speed, hierarchical synchronous reconfigurable array. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 125-134, February 1999.
16. D. M. Tullsen, S. Eggers, and H. M. Levy. Simultaneous multithreading: Maximizing on-chip parallelism. In Proceedings of the 22th Annual International Symposium on Computer Architecture, pages 392-403, 1995.
17. Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Virtex Series FPGAs, 1999.
18. Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Virtex Series FPGAs, 1999.