Floating point unit generation and evaluation for FPGAs

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn 2003-January, Issue , 2003, Pages 185-194

  Liang, Jian ^a   Tessier, R ^a   Mencer, O ^b  

^a University of Massachusetts   (United States)

^b IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

Algorithm design and analysis; Application software; Character generation; Delay; Educational institutions; Field programmable gate arrays; Libraries; Logic; Parallel processing; Throughput

Indexed keywords

APPLICATION PROGRAMS; C++ (PROGRAMMING LANGUAGE); COMPUTATION THEORY; COMPUTERS; DIGITAL ARITHMETIC; LIBRARIES; LOGIC GATES; PROGRAM COMPILERS; THROUGHPUT;

ALGORITHM DESIGN AND ANALYSIS; CHARACTER GENERATION; DELAY; EDUCATIONAL INSTITUTIONS; LOGIC; PARALLEL PROCESSING;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84942932890     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.2003.1227254     Document Type: Conference Paper

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