Residual stress in thick low-pressure chemical-vapor deposited polycrystalline SiC coatings on Si substrates

Journal of Applied Physics

Volumn 97, Issue 7, 2005, Pages

  Choi, D ^a   Shinavski, R J ^b   Steffier, W S ^b   Spearing, S M ^a,c  

^a Massachusetts Institute of Technology Cambridge   (United States)

^b Hyper Therm High Temperature Composites Inc   (United States)

^c UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

DEPOSITION TEMPERATURES; LAMINATED PLATE ANALYSIS; MICROELECTROMECHANICAL SYSTEMS (MEMS); ROOM TEMPERATURE;

CHEMICAL VAPOR DEPOSITION; COATINGS; COMPRESSIVE STRESS; GRAIN BOUNDARIES; MICROELECTROMECHANICAL DEVICES; RESIDUAL STRESSES; SILICON; SILICON CARBIDE; SILICON WAFERS; SUBSTRATES; TEMPERATURE DISTRIBUTION; THERMAL EXPANSION;

POLYCRYSTALLINE MATERIALS;

EID: 17544365233     PISSN: 00218979     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.1866495     Document Type: Article

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