A novel highly reliable low-power nano architecture when von Neumann augments Kolmogorov

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2004, Pages 167-177

  Beiu, Valeriu ^a  

^a Washington State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL SOLUTIONS; NANOELECTRONICS; POWER-EFFICIENT SOLUTIONS; SINGLE ELECTRON TECHNOLOGY (SET);

BOOLEAN FUNCTIONS; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTRON TUNNELING; FAULT TOLERANT COMPUTER SYSTEMS; LOGIC CIRCUITS;

NANOTECHNOLOGY;

EID: 11244285388     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2004.1342467     Document Type: Conference Paper

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