Realistic single-electron transistor modeling and novel CMOS/SET hybrid circuits

Proceedings of the IEEE Conference on Nanotechnology

Volumn 1, Issue , 2003, Pages 119-121

  Song, Ki Whan ^a   Baek, Gwanghyeon ^a   Lee, Sang Hoon ^a   Kim, Dae Hwan ^a   Kim, Kyung Rok ^a   Woo, Dong Soo ^a   Sim, Jae Sung ^a   Lee, Jong Duk ^a   Park, Byung Gook ^a  

^a Seoul National University   (South Korea)

Author keywords

Analytical models; Circuit stability; Degradation; MOSFET circuits; Quantum dots; Semiconductor device modeling; Single electron transistors; Temperature control; Temperature distribution; Threshold voltage

Indexed keywords

ANALYTICAL MODELS; CAPACITANCE MEASUREMENT; DEGRADATION; ELECTRIC NETWORK ANALYSIS; FIELD EFFECT TRANSISTORS; MOSFET DEVICES; NANOTECHNOLOGY; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICES; SEMICONDUCTOR QUANTUM DOTS; TEMPERATURE CONTROL; TEMPERATURE DISTRIBUTION; THRESHOLD VOLTAGE; TRANSIENTS; TRANSISTORS;

CIRCUIT STABILITY; COULOMB OSCILLATION; CURRENT BEHAVIORS; HIGH TEMPERATURE; HYBRID CIRCUIT; MOSFET CIRCUITS; PEAK TO VALLEY CURRENT RATIO; PEAK-TO-VALLEY RATIOS;

SINGLE ELECTRON TRANSISTORS;

EID: 11244305802     PISSN: 19449399     EISSN: 19449380     Source Type: Conference Proceeding    
DOI: 10.1109/NANO.2003.1231729     Document Type: Conference Paper

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