Split-Precharge Differential Noise-Immune Threshold Logic gate (SPD-NTL)

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2687, Issue , 2003, Pages 49-56

  Tatapudi, Suryanarayana ^a   Beiu, Valeriu ^a  

^a WASHINGTON STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC GATES; RECONFIGURABLE HARDWARE; SPURIOUS SIGNAL NOISE; THRESHOLD LOGIC; NEURAL NETWORKS;

DIFFERENTIAL LOGIC; DIFFERENTIAL THRESHOLD; LOGIC BLOCKS; NOISE IMMUNE; NOISE IMMUNITY; NOISE SUPPRESSION; PRE-CHARGE; STATE OF THE ART; ENHANCED PERFORMANCE; LOW POWER;

COMPUTER CIRCUITS; LOGIC GATES;

EID: 35248900335     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-44869-1_7     Document Type: Article

References (40)

1. Avellido, M.J., Quintana, J.M., Rueda, A., Jiménez, E.: A low-power CMOS threshold-gate. Electron. Lett. 31 (1995) 2157-2159
2. Beiu, V.: Ultra-fast noise immune CMOS threshold gates. Proc. MWSCAS'2000 vol. 3 (2000) 1310-1313.
3. Beiu, V.: Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith. U.S. Patent 6 205 458 (Mar. 20, 2001)
4. Beiu, V.: Logic gate having reduced power dissipation and method of operation thereof. U.S. Patent 6 259 275 (Jul. 10, 2001)
5. Bieu, V: On higher order noise immune perceptrons. Proc. IJCNN'2001 vol. 1 (2001) 246-251
6. Beiu, V.: Noise tolerant conductance-based logic gate and methods of operation and manufacturing thereof. U.S. Patent 6 430 585 (Aug. 6, 2002)
7. Beiu, V.: Low-power differential conductance-based logic gate and method of operation thereof. U.S. Patent allowed US/09/667 312 (Feb. 17, 2003)
8. Beiu, V., Quintana, J.M., Avedillo, M.J.: Review of differential threshold gate implementations. Proc. NCI'03 (May 2003)
9. Beiu, V.: On perceptron circuit complexity results and some practical applications. Proc. IJCNN'03 (Jul. 2003)
10. Beiu, V., Quintana, J.M., Avedillo, M.J.: VLSI implementations of threshold logic: a comprehensive survey. Accepted IEEE Trans. Neural Networks (Sep. 2003)
11. Bobba, S., Hajj, I.N.: Current-mode threshold logic gates. Proc. ICCD'2000 (2000) 235-240
12. Burns, J.R., Trenton, N.J., Powlus, R.A.: Threshold circuit utilizing field effect transistiors. U.S. Patent 3 260 863 (Jul. 12, 1966)
13. Celinski, P., Al-Sarawi, S., Abbott, D.: Delay analysis of neuron-MOS and capacitive threshold-logic. Proc. ICECS'2000 vol. 2 (2000) 932-935
14. Celinski, P., López, J.F., Al-Sarawi, S., Abbott, D.: Low power, high speed, charge recycling CMOS threshold logic gate. Electron. Lett. 37 (2001) 1067-1069
15. PCelinski, P., López, J.F., Al-Sarawi, S., Abbott, D.: Compact parallel (m, n) counters based on self-timed threshold logic. Electron. Lett. 38 (2002) 633-635
16. Fabbrizio, V., Raynal, F., Mariaud, X., Kramer, A., Colli, G.: Low-power, low-voltage conductance mode CMOS analog neuron. Proc. MicroNeuro'96 (1996) 111-115
17. Garcia, J.L., Ramos, J.F., Bohórquez, A.G.: A balanced capacitive threshold logic gate. Proc. DCIS'2000 [available at www.el.uma.es/Ppepefer/DCIS2000.pdf]
18. Gayles, E.S.: Data enabled logic circuits. U.S. Patent 6 078 196 (Jun. 20, 2000)
19. Huang, H.Y., Wang, T.N.: CMOS capacitor coupling logic (C3L) logic circuits. Proc. AP-ASIC'2000 (2000) 33-36
20. Johnson, M.G.: A symmetric CMOS NOR gate for high-speed applications. IEEE J. Solid-State Circuits 23 (1988) 1233-1236
21. Jung, S., Thewes, R., Scheiter, T., Goser, K.F., Weber, W.: A low-power and high-performance CMOS fingerprint sensing and encoding architecture. IEEE J. Solid-State Circuits 34 (1999) 978-984
22. Kistler, W.M., Gerstner, W., van Hemmen, J.L.: Reduction of the Hodgkin-Huxley equations to a single-variable threshold model. Neural Computation 9 (1997) 1015-1045
23. Kong, B.-S., Choi, J.-S., Lee, S.-J., Lee, K.: Charge recycling differential logic for low-power application. Proc. ISSCC'96 (1996) 302-303
24. Kotani, K., Shibata, T., Imai, M., Ohmi, T.: Clocked-controlled neuron-MOS logic gates. IEEE Trans. Circuits Syst. II 45 (1998) 518-522
25. Lan, M.F., Tammineedi, A., Geiger, R.: A new current mirror layout technique for improved matching characteristics. Proc. MWSCAS'99 (1999) 1126-1129
26. Lee, J., Park, J., Song, B., Kim, W.: Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic. IEEE J. Solid-State Circuits 36 (2001) 1276-1280
27. Lev, L.A.: Fast static cascode logic gate. U.S. Patent 5 438 283 (Aug. 1, 1995)
28. López, J.A.H., Tejero, J.G., Ramos, J.F., Bohórquez, A.G.: New types of digital comparators. Proc. ISCAS'95 vol. 1 (1995) 29-32
29. McCulloch, W.S., Pitts, W.: A logical calculus of the ideas immanent in nervous activity. Bull. Math. Biophysiol. 5 (1943) 115-133
30. Naffziger, S.D., Colon-Bonet, G., Fischer, T., Reidlinger, R., Sullivan, T.J., Grutkowski, T.: The implementation of the Itanium 2 microprocessor. IEEE J. Solid-State Circuits 37 (2002) 1448-1460
31. Ozdemir, H., Kepkep, A., Pamir, B., Leblebici, Y., Çilingiroǧlu, U.: A capacitive threshold-logic gate. IEEE J. Solid-State Circuits 31 (1996) 1141-1150
32. Pǎdure, M., Dan, C., Coţofaňa, S., Bodea, M., Vassiliadis, S.: Capacitive threshold logic: a designer perspective. Proc. CAS'99 vol. 1 (1999) 81-84
33. Pǎdure, M., Coţofanǎ, S., Dan, C., Bodea, M., Vassiliadis, S.: A new latch-based threshold logic family. Proc. CAS'01 vol. 2 (2001) 531-534
34. Park, J., Lee, J., Kim, W.: Current sensing differential logic: a CMOS logic for high reliability and flexibility. IEEE J. Solid-State Circuits 34 (1999) 904-908
35. Prange, S., Thewes, R., Wohlrab, E., Weber, W.: Circuit arrangement for realizing logic elements that can be represented by threshold value equations. U.S. Patent 5 991 789 (Nov. 23, 1999)
36. Ramos, J.F., López, J.A.H., Martín, M.J., Tejero, J.C., Bohórquez, A.G.: A threshold logic gate based on clocked coupled inverters. Intl. J. Electronics 84 (1998) 371-382
37. Shibata, T., Ohmi, T.: An intelligent MOS transistor featuring gate-level weighted sum and threshold operations. IEDM Technical Digest (1991) 919-922
38. Strandberg, R., Yuan, J.: Single input current-sensing differential logic (SCSDL). Proc. ISCAS'2000 vol. 1 (2000) 764-767
39. Tsividis, Y.P., Anastassiou, D.: Switched-capacitor neural networks. Electron. Lett. 23 (1987) 958-959
40. Weber, W., Prange, S.J., Thewes, R., Wohlrab, E., Luck, A.: On the application of neuron MOS transistor principle for modern VLSI design. IEEE Trans. Electron Devices 43 (1996) 1700-1708