A view from the bottom: Nanometer technology ac parametric failures-why, where, and how to detect

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2003-January, Issue , 2003, Pages 267-274

  Hawkins, Charles ^a   Keshavarzi, Ali ^a   Segura, Jaume ^a  

^a UNIVERSITY OF NEW MEXICO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRACKS; DESIGN FOR TESTABILITY; FAULT TOLERANCE; INTEGRATED CIRCUIT DESIGN; TESTING;

CIRCUIT PARAMETER; DEFECT-FREE; DESIGN RULES; FAILURE MECHANISM; NANOMETER TECHNOLOGY; PARAMETRIC FAILURE; STATISTICAL DISTRIBUTION; TEST PROCESS;

DEFECTS;

EID: 84971299971     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TSM.2005.1250121     Document Type: Conference Paper

References (30)

1. M. Alam and K. Smith, A phenomenological theory of correlated multiple soft-breakdown events in ultr-thin gate dielectrics, International Reliability Physics Symposium (IRPS), pp. 406-411, April 2003.
2. K. Baker, G. Grounthoud, M. Lousberg, I. Schanstra and C. Hawkins, Defect-based delay testing of resistive vias-contacts - a critical evaluation, International Test Conference (ITC), pp. 467-476, October 1999.
3. K. Bernstein, K. Carrig, C. Durham, P. Hansen, D. Hogenmiller, E. Nowak, and N. Rohrer, High Speed CMOS Design Styles, Kluwer Academic Publishers, 1998.
4. M. Breuer and S. Gupta, Process aggravated noise (PAN): New validation and test problems, International Test Conference (ITC), pp. 914-923, October 1996.
5. M. Bruce, V. Bruce, D. Epps, J. Wilcox, E. Cole, P. Tangyungyong and C. Hawkins, Soft Defect Localization (SDL) on ICs, International Symposium on Test and Failure Analysis (ISTFA), November 2002.
6. DDQ and other parametric data, Int. Test Conf. (ITC), pp. 92-100, Oct. 2001.
7. R. Degraeve, B. Kaczer, A. De Keersgieter and G. Groeseneken, Relation between breakdown mode and breakdown location in short channel NMOSFETs, International Reliability Physics Symposium (IRPS), pp. 360-366, May 2001.
8. A. Deutsch, et al., On-chip wiring design challenges for gigahertz operation, Proceeding of the IEEE, Vol. 89, No. 4, April 2001.
9. International Technology Roadmap for Semiconductors 2001 (http://public.itrs.net/).
10. K. Kana, K. Nose and T. Sakurai, Design impact of positive temperature dependence on drain current in sub-1V CMOS VLSIs, IEEE Journal of Solid State Circuits, pp. 1559-1564, October 2001.
11. C. Hawkins, J. Soden, A. Righter and J. Ferguson, Defect classes - An overdue paradigm for testing CMOS ICs, International Test Conference (ITC), pp. 413-424, October 1994.
12. DDQ, Int. Test Conf. (ITC), pp. 1051-1059, Oct. 2000.
13. A. Keshavarzi, K. Roy, J. Tschanz, S. Narendra, C. Hawkins, R. Daasch, M. Sachdev and V. De, Leakage and Process Variation in Current-Based Testing on Future CMOS Circuits, IEEE Design & Test of Computers, pp. 36-43, Fall 2002.
14. B. Krusman, R. Van Veen and K. Van Kaam, The future of delta IDDQ testing, Int. Test Conf. (ITC), pp. 101-110, Oct. 2002.
15. R. Madge, et al., Screening MinVDD Outliers Using Feed-Forward Voltage Testing, Int. Test Conf. (ITC), pp. 673-682, Oct. 2002.
16. DDQ testing, Int. Test Conf. (ITC), pp. 738-746, October 1999.
17. DDQ testing in deep submicron integrated circuits, Int. Test Conf. (ITC), pp. 724-729, October 1999.
18. S. Narendra, D. Antoniadis and V. De, Impact of using adaptive body bias to compensate die-to-die Vt variation on within-die Vt variation, International Symposium on Low Power Electronics and Design, pp. 229-232, 1999.
19. M. Orshansky, L. Millor, P. Chen, K. Keutzer and C. Hu, Impact of spatial intrachip gate length variability on the performance of hi-speed digital circuits, IEEE Transactions on Computer-Aided Design, Vol. 21, No. 5, May 2002.
20. W. Righter, C. Hawkins, J. Soden and P. Maxwell, CMOS IC Reliability Indicators and Burn-In Economics, International Test Conference (ITC), Washington D. C., November 1998.
21. R. Rodriguez, J. Stathis and B. Linder, Modeling and experimental verification of the effect of gate oxide breakdown on CMOS inverters, International Reliability Physics Symposium (IRPS), pp. 11-16, April 2003.
22. J. Segura, A. Keshavarzi, J. Soden and C. Hawkins, Parametric failures in CMOS ICs - A defectbased analysis, International Test Conference (ITC), October 2002.
23. J. Segura and C. Hawkins, CMOS Electronics: How it Works, How it Fails, IEEE Press/Wiley, Pub in Fall 2003.
24. DDQ testing of CMOS opens: An experimental study, International Test Conference (ITC), pp. 479-489, October 1995.
25. D. Sylvester and K. Keutzer, Impact of small process geometries on microarchitectures in systems on a chip, Proceedings of the IEEE, Vol. 89, No 4., pp. 467-489, April 2001.
26. T CMOS, IEEE Journal of Solid-State Circuits, vol. 37, no. 11, p. 1421-32, Nov. 2002
27. C. Visweswariah, Death, taxes, and failing chips, Design Auto. Conf., pp. 343-347, June 2003.
28. M. Weber, My head hurts, my timing stinks, and I don t love on-chip variation, Synopsis User Group Meeting, SNUGBoston02, 2002.
29. B. Weir, et al., Ultra-thin gate dielectrics: they break down, but do they fail?, International Electron Device Meeting (IEDM), pp. 73-76, 1997.
30. A. Wong, Microlithography: trends, challenges, solutions, and their impact on design, IEEE Micro, pp. 12-21, March-April 2003.