On nanoelectronic architectural challenges and solutions

2004 4th IEEE Conference on Nanotechnology

Volumn , Issue , 2004, Pages 628-631

  Beiu, Valeriu ^a   Rückert, Ulrich ^b   Roy, Sandip ^a   Nyathi, Jabulani ^a  

^a WASHINGTON STATE UNIVERSITY   (United States)

^b UNIVERSITY OF PADERBORN   (Germany)

Author keywords

Computer architectures; Nanotechnology; Semiconductor devices

Indexed keywords

BOOLEAN ALGEBRA; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; CORRELATION METHODS; ELECTRONIC EQUIPMENT; INTEGRATED CIRCUITS; MATRIX ALGEBRA; NETWORK PROTOCOLS; SEMICONDUCTOR DEVICES; SPREADSHEETS;

COMMUNICATION PROBLEMS; NANOELECTRONIC ARCHITECTURES; NANOELECTRONIC DEVICES; SECOND-ORDER DEFECTS;

NANOTECHNOLOGY;

EID: 20344370026     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. The International Technology Roadmap for Semiconductors (ITRS), 2003. Available: http://public.itrs.net/
2. R. Compañó, L. Molenkamp, and D.J. Paul (Eds.), Technology Roadmap for Nanoelectronics, European Commission, IST Programme, Future and Emerging Technologies, 2000. Available: http://www.cordis.lu/esprit/src/melna- rm.htm
3. V. Beiu, "The Next Generation of Neural Network Chips: Shaping the Hardware Solutions for the Next Millennium," Special Session, Intl. Symp. Engineering of Intelligent Sys. EIS'98, Tenerife, Spain, Feb. 1998.
4. "Silicon Nanoelectronics and Beyond," SCR-NNI Workshop, Portland, Oct. 2003. http://www.src.org/member/event/e002238/
5. V. Beiu, J. M. Quintana, and M. J. Avedillo, "Threshold Gates: Past, Present, and Future," Special Session, Intl. Workshop Artif. & Natural Neural Networks IWANN'03, Mahon, Spain, Jun. 2003.
6. V. Beiu, and U. Rückert, "Neural Inspired Architectures for Nanoelectronics," Special Workshop, Neural Inform. Proc. Sys. NIPS*03, Whistler, Canada, Dec. 2003. Available: http://www. eecs.wsu.edu/~vbeiu/workshop_nips03/
7. U. Rücken, and V. Beiu, "Brain Inspired Emerging Architectures: Design and Technological Challenges," Special Session, Intl. Joint Conf. Neural Networks IJCNN'04, Budapest, Hungary, Jul. 2004.
8. V. Beiu, and U. Rücken (Eds.), Emerging Brain-Inspired Nano-Architectures, 2004, in progress.
9. V. Beiu, M. Sulieman, and S. Roy, "Majority multiplexing: Practical applications to nanoscale computations and communication," Proc. Application-specific Sys., Arch. & Processors ASAP'04, Sep. 2004, to appear.
10. Centers for Neural-Inspired Nano Architectures See http://www.cnina.org/