Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors

Proceedings of the IEEE Conference on Nanotechnology

Volumn 2, Issue , 2003, Pages 516-519

  Schmid, A ^a   Leblebici, Y ^a  

^a EPFL   (Switzerland)

Author keywords

Circuit simulation; Circuits and systems; Design methodology; Digital systems; Fault tolerance; Guidelines; Nanoscale devices; Robustness; Single electron transistors; SPICE

Indexed keywords

CIRCUIT SIMULATION; DESIGN; DIGITAL DEVICES; FAULT TOLERANCE; FIELD EFFECT TRANSISTORS; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; ROBUSTNESS (CONTROL SYSTEMS); SPICE; TRANSIENTS; TRANSISTORS;

CIRCUITS AND SYSTEMS; DESIGN METHODOLOGY; DIGITAL SYSTEM; GUIDELINES; NANOSCALE DEVICE;

SINGLE ELECTRON TRANSISTORS;

EID: 20344374324     PISSN: 19449399     EISSN: 19449380     Source Type: Conference Proceeding    
DOI: 10.1109/NANO.2003.1230960     Document Type: Conference Paper

References (6)

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