-
2
-
-
0036507205
-
Extending the road beyond CMOS
-
Feb.
-
J. A. Hutchby, G. I. Bourianoff, V. V. Zhirnov, and J. E. Brewer, "Extending the road beyond CMOS," IEEE Circuits Devices Mag., vol. 18, pp. 28-41, Feb. 2002.
-
(2002)
IEEE Circuits Devices Mag.
, vol.18
, pp. 28-41
-
-
Hutchby, J.A.1
Bourianoff, G.I.2
Zhirnov, V.V.3
Brewer, J.E.4
-
4
-
-
0035718150
-
A multiple-valued logic with merged single-electron and MOS transistors
-
H. Inokawa, A. Fujiwara, and Y. Takahashi, "A multiple-valued logic with merged single-electron and MOS transistors," in IEDM Tech. Dig., 2001, pp. 147-150.
-
IEDM Tech. Dig., 2001
, pp. 147-150
-
-
Inokawa, H.1
Fujiwara, A.2
Takahashi, Y.3
-
5
-
-
0033116234
-
Single-electron memory for giga-to-tera bit storage
-
Apr.
-
Y. Yano et al., "Single-electron memory for giga-to-tera bit storage," Proc. IEEE, vol. 87, pp. 633-651, Apr. 1999.
-
(1999)
Proc. IEEE
, vol.87
, pp. 633-651
-
-
Yano, Y.1
-
6
-
-
0006825518
-
Coulomb blockade memory using integrated single-electron transistor/metal-oxide semiconductor transistor grain cells
-
Dec.
-
Z. A. K. Durrani, A. C. Irvine, and H. Ahmed, "Coulomb blockade memory using integrated single-electron transistor/metal-oxide semiconductor transistor grain cells," IEEE Trans. Electron Devices, vol. 47, pp. 2334-2339, Dec. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, pp. 2334-2339
-
-
Durrani, Z.A.K.1
Irvine, A.C.2
Ahmed, H.3
-
7
-
-
0036057138
-
Few electron devices: Toward hybrid CMOS-SET integrated circuits
-
A. M. Ionescu, M. Declerq, S. Mahapatra, K. Banerjee, and J. Gautier, "Few electron devices: toward hybrid CMOS-SET integrated circuits," in Proc. DAC 2002, pp. 88-93.
-
Proc. DAC 2002
, pp. 88-93
-
-
Ionescu, A.M.1
Declerq, M.2
Mahapatra, S.3
Banerjee, K.4
Gautier, J.5
-
9
-
-
0036923558
-
Modeling and analysis of power dissipation in single electron logic
-
S. Mahapatra, A. M. Ionescu, K. Banerjee, and M. J. Declerq, "Modeling and analysis of power dissipation in single electron logic," in IEDM Tech. Dig., 2002, pp. 323-326.
-
IEDM Tech. Dig., 2002
, pp. 323-326
-
-
Mahapatra, S.1
Ionescu, A.M.2
Banerjee, K.3
Declerq, M.J.4
-
10
-
-
0042026550
-
Programmable single-electron transistor logic for future low-power intelligent Si LSI: Proposal and room temperature operation
-
July
-
K. Uchida, J. Koga, R. Ohba, and A. Toriumi, "Programmable single-electron transistor logic for future low-power intelligent Si LSI: proposal and room temperature operation," IEEE Trans. Electron Devices, vol. 50, pp. 1623-1630, July 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, pp. 1623-1630
-
-
Uchida, K.1
Koga, J.2
Ohba, R.3
Toriumi, A.4
-
11
-
-
2942758197
-
-
BSIM Homepage. UC Berkeley, CA
-
BSIM Homepage. UC Berkeley, CA. [Online] Available: http://www-device.Eecs.Berkeley.EDU/-ptm
-
-
-
-
12
-
-
0007836179
-
Negative differential resistance due to single-electron switching
-
C. P. Heij, D. C. Dixon, P. Hadley, and J. E. Mooij, "Negative differential resistance due to single-electron switching," Appl. Phys. Lett., vol. 74, no. 7, pp. 1042-1044, 1999.
-
(1999)
Appl. Phys. Lett.
, vol.74
, Issue.7
, pp. 1042-1044
-
-
Heij, C.P.1
Dixon, D.C.2
Hadley, P.3
Mooij, J.E.4
-
13
-
-
0346778737
-
A CAD framework for co-design and analysis of CMOS-SET hybrid integrated circuits
-
S. Mahapatra, K. Banerjee, F. Pegeon, and A. M. Ionescu, "A CAD framework for co-design and analysis of CMOS-SET hybrid integrated circuits," in Proc. ICCAD 2003, pp. 497-502.
-
Proc. ICCAD 2003
, pp. 497-502
-
-
Mahapatra, S.1
Banerjee, K.2
Pegeon, F.3
Ionescu, A.M.4
-
14
-
-
0004326220
-
-
SILVACO Inc.
-
SMARTSPICE User's Manual. SILVACO Inc., [Online] Available: http://www.silvaco.com
-
SMARTSPICE User's Manual
-
-
-
15
-
-
0034429730
-
CMOS circuit technology for subambient temperature operation
-
I. Aller et al., "CMOS circuit technology for subambient temperature operation," in Proc. ISSCC 2000, pp. 214-215.
-
Proc. ISSCC 2000
, pp. 214-215
-
-
Aller, I.1
|