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Volumn 25, Issue 6, 2004, Pages 411-413

Hybrid SETMOS architecture with Coulomb Blockade oscillations and high current drive

Author keywords

Circuit simulation; CMOS SET hybrid technology; Negative differential resistance (NDR) device; Semiconductor device model; Single electron transistor (SET)

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES;

EID: 2942720952     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.828558     Document Type: Letter
Times cited : (37)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.