Hybrid SETMOS architecture with Coulomb Blockade oscillations and high current drive

IEEE Electron Device Letters

Volumn 25, Issue 6, 2004, Pages 411-413

  Ionescu, Adrian Mihai ^a   Mahapatra, Santanu ^a   Pott, Vincent ^a  

^a EPFL   (Switzerland)

Author keywords

Circuit simulation; CMOS SET hybrid technology; Negative differential resistance (NDR) device; Semiconductor device model; Single electron transistor (SET)

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES;

COULOMB BLOCKADE OSCILLATIONS; SINGLE ELECTRON TRANSISTOR;

MOSFET DEVICES;

EID: 2942720952     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.828558     Document Type: Letter

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