Independent test sequence compaction through integer programming

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2003, Pages 380-386

  Drineas, Petros ^a   Makris, Yiorgos ^b  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^b Yale University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; INTEGER PROGRAMMING; LINEAR PROGRAMMING; POLYNOMIAL APPROXIMATION; SEQUENTIAL CIRCUITS; TIME DOMAIN ANALYSIS; VECTOR QUANTIZATION;

BENCHMARK CIRCUITS; INDEPENDENT TEST SEQUENCE COMPACTION; POLYNOMIAL TIME APPROXIMATION ALGORITHM; RANDOMIZED ROUNDING;

INTEGRATED CIRCUIT TESTING;

EID: 0345413237     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (35)

1. F. Corno, P. Prinetto, M. Rebaudegno, and M. Sonza Reorda, "New static compacion techniques of test sequences for sequential circuits," in European Design and Test Conference, 1997, pp. 37-43.
2. J. Raik, A. Jutman, and R. Ubar, "Fast static compaction of tests composed of independent sequences: Basic properties and comparison of methods," International Conference on Electronics, Circuits, and Systems, pp. 445-448, 2002.
3. P. Raghavan and C. Thompson, "Randomized rounding: A technique for provably good algorithms and algorithmic proofs," Combinatorica, vol. 7, no. 4, pp. 365-374, 1987.
4. "ISCAS'89 benchmark circuits information," Available from http://www.cbl.ncsu.edu
5. M. H. Schulz, E. Trischler, and T. M. Sarfert, "SOCRATES: a highly efficient automatic test pattern generation system," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 1, pp. 126-137, 1988.
6. J. A. Waicukauski, P.A. Shupe, D. J. Giramma, and A. Matin, "ATPG for ultra-large structured designs," in International Test Conference, 1990, pp. 44-51.
7. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, 1990.
8. J-S. Chang and C-S. Lin, "Test set compaction for combinational circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 11, pp. 1370-1378, 1995.
9. Ilker Hamzaoglu and Janak H. Patel, "Test set compaction algorithms for combinational circuits," in International Conference on Computer-Aided Design, 1998, pp. 283-289.
10. P. Goel and B. C. Rosales, "Test generation and dynamic compaction of tests," in Digest of Papers, Test Conference, 1979, pp. 189-192.
11. S. B. Akers, C. Joseph, and B. Krishnamurthy, "On the role of independent fault sets in the generation of minimal test sets," in International Test Conference, 1987, pp. 1100-1107.
12. G-J. Tromp, "Minimal test sets for combinational logic," in International Test Conference, 1991, pp. 204-209.
13. I. Pomeranz, L. N. Reddy, and S. M. Reddy, "COMPACTEST: a method to generate compact test sets for combinational circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 7, pp. 1040-1049, 1993.
14. S. Kajihara, I. Pomeranz, K. Kinoshita, and S. M. Reddy, "Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 12, pp. 1496-1504, 1992.
15. J. P. Marques Silva, "Integer programming models for optimization problems in test generation," in Asia South Pacific Design Automation Conference, 1998, pp. 481-487.
16. T. M. Niermann, R. K. Roy, J. H. Patel, and J. A. Abraham, "Test compaction for sequential circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 11, no. 2, pp. 260-267, 1992.
17. M. H. Hsiao, E. M. Rudnick, and J. H. Patel, "Fast static compaction algorithms for sequential circuit test vectors," IEEE Transactions on Computers, vol. 48, no. 3, pp. 311-322, 1999.
18. M. Hsiao and S. T. Chakradhar, "State relaxation based subsequence removal for fast static test compaction," in Design Automation and Test in Europe Conference, 1998, pp. 577-582.
19. I. Pomeranz, S. M. Reddy, and R. Guo, "Static test compaction for synchronous sequential circuits based on vector restoration," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, no. 7, pp. 1040-1049, 1999.
20. S. K. Bommu, S. T. Chakradhar, and K. B. Doreswamy, "Static test sequence compaction based on segment reordering and accelerated vector restoration," in International Test Conference, 1998, pp. 954-961.
21. X. Lin, W.-T. Cheng, I. Pomeranz, and S. M. Reddy, "SIFAR: static test compaction for synchronous sequential circuits based on single fault restoration," in VLSI Test Symposium, 2000, pp. 205-212.
22. I. Pomeranz and S. M. Reddy, "Procedures for static compaction of test sequences for synchronous sequential circuits," IEEE Transactions on Computers, vol. 49, no. 6, pp. 596-607, 2000.
23. I. Pomeranz, S. M. Reddy, and R. Guo, "Vector replacement to improve static-test compaction for synchronous sequential circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, pp. 336-342, 2001.
24. I. Pomeranz and S. M. Reddy, "Forward-looking fault simulation for improved static compaction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 10, pp. 1262-1265, 2001.
25. I. Pomeranz and S. M. Reddy, "On generating compact test sequences for synchronous sequential circuits," in European Design Automation Conference, 1995, pp. 105-110.
26. A. Ragunathan and S. T. Chakradhar, "Acceleration techniques for dynamic vector compaction," in International Conference on Computer-Aided Design, 1995, pp. 310-317.
27. T. J. Lambert and K. K. Saluja, "Methods for dynamic vector compaction in sequential test generation," in International Conference on VLSI Design, 1996, pp. 166-169.
28. I. Pomeranz and S. M. Reddy, "Dynamic test compaction for synchronous sequential circuits using static compaction techniques," in Fault Tolerant Computing Symposium, 1996, pp. 53-61.
29. R. Bevacqua, L. Guerazzi, F. Ferrandi, and F. Fummi, "Implicit test sequences compaction for decreasing test application cost," in International Conference on Computer Design, 1996, pp. 384-389.
30. E. M. Rudnick and J. H. Patel, "Efficient techniques for dynamic test sequence compaction," IEEE Transactions on Computers, vol. 48, no. 3, pp. 323-330, 1999.
31. R. Guo, S. M. Reddy, and I. Pomeranz, "PROPTEST: a property based test pattern generator for sequential circuits using test compaction," in Design Automation Conference, 1999, pp. 653-659.
32. W. Hoeffding, "Probability inequalities for sums of bounded random variables," American Statistical Association Journal, pp. 13-30, March 1962.
33. L.G. Khachiyan, "A polynomial-time algorithm for linear programming," Soviet Math. Dokl., vol. 20, no. 1, pp. 191-194, 1979.
34. N. Karmarkar, "A new polynomial-time algorithm for linear programming," Proceedings of the Annual Symposium on Theory of Computing, pp. 302-311, 1984.
35. "Test sequence tables used in [1]," Available from http://www.cad.polito.it/tools.