Vector replacement to improve static-test compaction for synchronous sequential circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 2, 2001, Pages 336-342

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^b  

^a PURDUE UNIVERSITY   (United States)

^b IA United States   (United States)

Author keywords

Static test compaction; Synchronous sequential circuits

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; FAULT TREE ANALYSIS; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS;

STATIC COMPACTION PROCEDURE; STATIC TEST COMPACTION; SYNCHRONOUS SEQUENTIAL CIRCUIT; VECTOR REPLACEMENT;

SEQUENTIAL CIRCUITS;

EID: 0035248228     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.908476     Document Type: Article

References (13)

1. Compaction of ATPG-generated test sequences for sequential circuits
2. Time-efficient automatic test pattern generation systems
3. On static compaction of test sequences for synchronous sequential circuits
4. New static compaction techniques of test sequences for sequential circuits
5. Fast algorithms for static compaction of sequential circuit test vectors
6. Vector restoration based static compaction of test sequences for synchronous sequential circuits
7. State relaxation based subsequence removal for fast static compaction in sequential circuits
8. Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration
9. An approach for improving the levels of C compaction achieved by vector omission
10. Random pattern testing for sequential circuits revisited
11. Sequential circuit test generation using dynamic state traversal
12. On the effects of test compaction on defect coverage
13. HITEC: A test generation package for sequential circuits