Fast static compaction algorithms for sequential circuit test vectors

IEEE Transactions on Computers

Volumn 48, Issue 3, 1999, Pages 311-322

  Hsiao, Michael S ^a,b   Rudnick, Elizabeth M ^a,c   Patel, Janak H ^a,c  

^a IEEE   (United States)

^b RUTGERS UNIVERSITY   (United States)

^c University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT SIMULATION; SEQUENTIAL CIRCUIT TEST VECTORS; STATIC COMPACTION ALGORITHMS;

ALGORITHMS; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; VECTORS;

SEQUENTIAL CIRCUITS;

EID: 0033098901     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.754997     Document Type: Article

References (12)

1. T.M. Niermann, R.K. Roy, J.H. Patel, and J.A. Abraham, "Test Compaction for Sequential Circuits," IEEE Trans. Computer-Aided Design, vol. 11, no. 2, pp. 260-267, Feb. 1992.
2. B. So, "Time-Efficient Automatic Test Pattern Generation System," PhD thesis, Electrical Eng. Dept., Univ. of Wisconsin at Madison, 1994.
3. I. Pomeranz and S.M. Reddy, "On Static Compaction of Test Sequences for Synchronous Sequential Circuits," Proc. Design Automation Conf., pp. 215-220, June 1996.
4. T.M. Niermann and J.H. Patel, "HITEC: A Test Generation Package for Sequential Circuits," Proc. European Conf. Design Automation (EDAC), pp. 214-218, 1991.
5. T.M. Niermann and J.H. Patel, "Method for Automatically Generating Test Vectors for Digital Integrated Circuits," U.S. Patent No. 5,377,197, Dec. 1994.
6. F. Brglez, D. Bryan, and K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," Proc. Int'l Symp. Circuits and Systems, pp. 1,929-1,934, 1989
7. T.H. Cormen, C.E. Leiserson, and R.L. Rivest, Introduction to Algorithms. Cambridge, Mass.: The MIT Press, 1990.
8. E.M. Rudnick, J.H. Patel, G.S. Greenstein, and T.M. Niermann, "A Genetic Algorithm Framework for Test Generation," IEEE Trans. Computer-Aided Design, vol. 16, no. 9, pp. 1,034-1,044, Sept. 1997.
9. E.M. Rudnick, "Simulation-Based Techniques for Sequential Circuit Testing," PhD dissertation, Dept. of Electrical and Computer Eng., Technical Report CRHC-94-14/UILU-ENG-94-2229, Univ. of Illinois, Aug. 1994.
10. M.S. Hsiao, E.M. Rudnick, and J.H. Patel, "Automatic Test Generation Using Genetically-Engineered Distinguishing Sequences," Proc. VLSI Test Symp., pp. 216-223, 1996.
11. M.S. Hsiao, E.M. Rudnick, and J.H. Patel, "Sequential Circuit Test Generation Using Dynamic State Traversal," Proc. European Design and Test Conf., pp. 22-28, 1997.
12. E.M. Rudnick and J.H. Patel, "Simulation-Based Techniques for Dynamic Test Sequence Compaction," Proc. Int'l Conf. Computer-Aided Design, pp. 67-73, 1996.