Methods for dynamic test vector compaction in sequential test generation

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1996, Pages 166-169

  Lambert, Timothy John ^a   Saluja, Kewal K ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; HEURISTIC METHODS; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS; RANDOM PROCESSES; VECTORS;

BEST RANDOM FILL; DYNAMIC LINEAR TIME COMPLEXITY ALGORITHMS; DYNAMIC TEST VECTOR COMPACTION; SEQUENTIAL BENCHMARK CIRCUITS; SEQUENTIAL CIRCUIT TEST PATTERN GENERATION; WEIGHTED DETERMINISTIC FILL;

SEQUENTIAL CIRCUITS;

EID: 0029716610     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)