Implicit test sequences compaction for decreasing test application cost

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1996, Pages 384-389

  Bevacqua, R ^a   Ferrandi, F ^a   Fummi, F ^a   Guerrazzi, L ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BINARY SEQUENCES; DATA STORAGE EQUIPMENT; DECISION TABLES; ELECTRIC FAULT CURRENTS; SEQUENTIAL CIRCUITS;

BINARY DECISION DIAGRAMS (BDD); TEST PATTERN STORAGE; TEST SEQUENCES COMPACTION;

INTEGRATED CIRCUIT TESTING;

EID: 0030413606     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)