Acceleration techniques for dynamic vector compaction

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1995, Pages 310-317

  Raghunathan, Anand ^a   Chakradhar, Srimat T ^a  

^a PRINCETON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; ELECTRIC NETWORK SYNTHESIS; LOGIC DESIGN; SEQUENTIAL CIRCUITS; VECTORS; VLSI CIRCUITS;

DYNAMIC VECTOR COMPACTION; FAULT SIMULATION;

LOGIC CIRCUITS;

EID: 0029544860     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)