Optimization of Scannable Latches for Low Energy

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 5, 2003, Pages 778-788

  Zyuban, Victor ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Circuit tuning; Curcuit power; Energy; Flip flop; Glitching; Latch

Indexed keywords

ENERGY DISSIPATION; OPTIMIZATION; SCANNING; SWITCHING CIRCUITS; TUNING;

GLITCHING;

FLIP FLOP CIRCUITS;

EID: 0142227166     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.814322     Document Type: Article

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