Timing characterization of dual-edge triggered flip-flops

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 538-541

  Nedovic, N ^a   Aleksic, M ^a   Oklobdzija, V G ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRONIC TIMING DEVICES; PROGRAM PROCESSORS; TRIGGER CIRCUITS;

DUAL-EDGE TRIGGERED FLIP FLOPS (DETFF);

FLIP FLOP CIRCUITS;

EID: 0035183783     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. A 1.2 GHz alpha microprocessor with 44.8GB/s chip pin bandwidth
2. A 1-GHz single-issue 64b powerPC processor
3. Analysis of power dissipation in double edge-triggered flip-flops
4. Low-power double-edge triggered flip-flop
5. Double-edge-triggered D-flip-flops for high-speed CMOS circuits
6. Low power design using double edge triggered flip-flops
7. Low power, testable dual edge triggered flip-flops
8. Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems