Activity-sensitive flip-flop and latch selection for reduced energy

Proceedings - 2001 Conference on Advanced Research in VLSI, ARVLSI 2001

Volumn , Issue , 2001, Pages 59-74

  Heo, Seongmoo ^a   Krashinsky, R ^a   Asanovic K ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Clocks; Delay; Energy consumption; Flip flops; Latches; Signal design; Tellurium; Threshold voltage; Timing; Very large scale integration

Indexed keywords

CLOCKS; DESIGN; ENERGY UTILIZATION; TELLURIUM; TELLURIUM COMPOUNDS; THRESHOLD VOLTAGE; VLSI CIRCUITS;

ACTIVATION PATTERNS; DELAY; OPERATING REGIMES; PROCESSOR DATAPATH; REDUCED ENERGY; SIGNAL DESIGN; SPEED REQUIREMENT; TIMING;

FLIP FLOP CIRCUITS;

EID: 84951809300     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARVLSI.2001.915551     Document Type: Conference Paper

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