Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 56-59

  Dao, H Q ^a   Nowka, K ^a   Oklobdzija, V G ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Clocked timing elements; Process variation; Voltage scaling

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC DELAY LINES; ELECTRIC POWER SUPPLIES TO APPARATUS; TIME VARYING NETWORKS; TIMING CIRCUITS; VLSI CIRCUITS; VOLTAGE MEASUREMENT;

DYNAMIC VOLTAGE SCALING; PROCESS PARAMETER VARIATION;

FLIP FLOP CIRCUITS;

EID: 0034878683     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/383082.383094     Document Type: Conference Paper

References (5)

1. Dynamic flip-flop with improved power
2. Sense amplifier-based flip-flop
3. Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
4. Embedded power supply for low-power DSP
5. A 2.2W, 80MHz superscalar RISC microprocessor