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Volumn , Issue , 1998, Pages 233-238

Latches and flip-flops for low power systems

Author keywords

[No Author keywords available]

Indexed keywords


EID: 0342778397     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1109/9780470545058.sect7     Document Type: Chapter
Times cited : (15)

References (12)
  • 1
    • 0028448788 scopus 로고
    • Power consumption estimation in CMOS VLSI chips
    • voi
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    • (1994) IEEE Journal of Solid State Circuits , vol.29 , pp. 663-670
    • Liu, D.1    Svensson, C.2
  • 3
    • 0002661154 scopus 로고    scopus 로고
    • Low power circuit techniques
    • M. Pedram and J. Rabaey, editors, Kluwer
    • C. Svensson and D. Liu, “Low power circuit techniques,” in Low Power Design Methodologies, M. Pedram and J. Rabaey, editors, Kluwer, 1996.
    • (1996) Low Power Design Methodologies
    • Svensson, C.1    Liu, D.2
  • 4
    • 0029255748 scopus 로고
    • A 300 MHz 64b quad-issue CMOS microprocessor
    • W. Bowhill et al., “A 300 MHz 64b quad-issue CMOS microprocessor,” ISSCC Digest of Technical Papers, 1995, pp. 182-183.
    • (1995) ISSCC Digest of Technical Papers , pp. 182-183
    • Bowhill, W.1
  • 6
    • 0025445461 scopus 로고
    • Race-free clocking of CMOS pipelines using a simple global clock
    • D. R. Renshaw and C. H. Lau, “Race-free clocking of CMOS pipelines using a simple global clock,” IEEE Journal of Solid State Circuits, voi. 25, 1990, pp. 766-769.
    • (1990) IEEE Journal of Solid State Circuits , vol.25 , pp. 766-769
    • Renshaw, D.R.1    Lau, C.H.2
  • 7
    • 0030828211 scopus 로고    scopus 로고
    • New single-clock CMOS latches and flipflops with improved speed and power savings
    • J. Yuan and C. Svensson, “New single-clock CMOS latches and flipflops with improved speed and power savings,” IEEE Journal of Solid State Circuits, voi. 32, 1997, pp. 62-69.
    • (1997) IEEE Journal of Solid State Circuits , vol.32 , pp. 62-69
    • Yuan, J.1    Svensson, C.2
  • 8
    • 0030081925 scopus 로고    scopus 로고
    • A 160MHz 32b 0.5W CMOS RISC microprocessor
    • J. Montanaro et al., “A 160MHz 32b 0.5W CMOS RISC microprocessor,” ISSCC Digest of Technical Papers, 1996, pp. 214-215.
    • (1996) ISSCC Digest of Technical Papers , pp. 214-215
    • Montanaro, J.1
  • 9
    • 0028454894 scopus 로고
    • Low power design using double edge triggered flip-flops
    • R. Hossain, L. D. Wronski, and A. Albicki, “Low power design using double edge triggered flip-flops,” IEEE Tr. on VLSI Systems, voi. 2, 1994, pp. 261-265.
    • (1994) IEEE Tr. On VLSI Systems , vol.2 , pp. 261-265
    • Hossain, R.1    Wronski, L.D.2    Albicki, A.3
  • 10
    • 0026207089 scopus 로고
    • A novel implementation of double-edge triggered flip-flop for high speed CMOS circuits
    • M. Afghahi and J. Yuan, “A novel implementation of double-edge triggered flip-flop for high speed CMOS circuits,” IEEE Journal of Solid State Circuits, voi. 26, 1991, pp. 1168-1170.
    • (1991) IEEE Journal of Solid State Circuits , vol.26 , pp. 1168-1170
    • Afghahi, M.1    Yuan, J.2
  • 11
    • 0031189144 scopus 로고    scopus 로고
    • Low-power logic styles: CMOS versus pass-transistor logic
    • R. Zimmermann and W. Fichtner, “Low-power logic styles: CMOS versus pass-transistor logic,” IEEE Journal of Solid State Circuits, voi. 32, 1997, pp. 1079-1090.
    • (1997) IEEE Journal of Solid State Circuits , vol.32 , pp. 1079-1090
    • Zimmermann, R.1    Fichtner, W.2
  • 12
    • 85051971035 scopus 로고
    • Austria Microsystems International, Dec
    • “0.8 pm CMOS process parameters,” Austria Microsystems International, Dec. 1994.
    • (1994) 0.8 Pm CMOS Process Parameters


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.