Low thermal-budget process of sputtered-PZT capacitor over multilevel metallization

IEEE Transactions on Electron Devices

Volumn 50, Issue 10, 2003, Pages 2081-2087

  Inoue, Naoya ^a   Nakura, Takeshi ^b   Hayashi, Yoshihiro ^a  

^a NEC CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

FeRAM; Ferroelectric memories; PZT; Sputtering

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; ELECTRODES; METALLIZING; RANDOM ACCESS STORAGE; SPUTTER DEPOSITION; TEMPERATURE;

FERROELECTRIC CAPACITORS; FERROELECTRIC PEROVSKITE PHASE; FERROELECTRIC RANDOM ACCESS MEMORY; LOW THERMAL-BUDGET PROCESS; NONFERROELECTRIC PYROCHLORE PHASE;

FERROELECTRIC MATERIALS;

EID: 0141940280     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.816548     Document Type: Article

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