Advanced 0.5 μm FRAM device technology with full compatibility of half-micron CMOS logic device

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1997, Pages 613-616

  Yamazaki, Tatsuya ^a   Inoue, Ken ichi ^a   Miyazawa, Hisashi ^a   Nakamura, Mitsuhiro ^a   Sashida, Naoya ^a   Satomi, Rei ^a   Kerry, Andrew ^a   Katoh, Yoshikazu ^a   Noshiro, Hideyuki ^a   Takai, Kazuaki ^a   Shinohara, Rika ^a   Ohno, Chikai ^a   Nakajima, Tetsuya ^a   Furumura, Yuji ^a   Kawamura, Seiichiro ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FERROELECTRIC MEMORY TECHNOLOGY; FERROELECTRIC RANDOM ACCESS MEMORY (FRAM);

CMOS INTEGRATED CIRCUITS; DEGRADATION; DEPOSITION; DIELECTRIC FILMS; FERROELECTRIC DEVICES; LOGIC DEVICES;

RANDOM ACCESS STORAGE;

EID: 84886448059     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)