A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 11, 1996, Pages 1625-1633

  Koike, Hiroki ^b,c,d,e,f   Otsuki, Tetsuya ^b,g   Kimura, Tohru ^a,b,h,i   Fukuma, Masao ^a,b,e,j,k,l   Hayashi, Yoshihiro ^b,j,l,m,n   Maejima, Yukihiko ^b,h,l,o   Amanuma, Kazushi ^b   Tanabe, Nobuhiro ^b   Matsuki, Takeo ^b   Saito, Shinobu ^b   Takeuchi, Tsuneo ^b   Kobayashi, Souta ^b   Kunio, Takemitsu ^b   Hase, Takashi ^b   Miyasaka, Yoichi ^b   Shohata, Nobuaki ^b   Takada, Masahide ^a  

^a IEEE

^b NEC CORPORATION   (Japan)

^c TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^d ULSI Device Development Laboratories

^e Microlectron Research Laboratories

^f Info Commun E

^g KYOTO UNIVERSITY   (Japan)

^h UNIVERSITY OF TOKYO   (Japan)

ⁱ MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^j KEIO UNIVERSITY   (Japan)

^k VLSI Development Division

^l JAPAN SOCIETY OF APPLIED PHYSICS   (Japan)

^m Rutgers State University   (United States)

ⁿ DARTMOUTH COLLEGE   (United States)

^o WASEDA UNIVERSITY   (Japan)

more..

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CAPACITORS; CMOS INTEGRATED CIRCUITS; FERROELECTRIC DEVICES; INTEGRATED CIRCUIT MANUFACTURE; NONVOLATILE STORAGE; RANDOM ACCESS STORAGE;

CIRCUIT TECHNOLOGIES; MEMORY CELL CAPACITANCE; NONDRIVEN CELL PLATE; NONVOLATILE FERROELECTRIC MEMORY; VOLTAGE GENERATOR CIRCUIT;

SEMICONDUCTOR STORAGE;

EID: 0030284494     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/jssc.1996.542307     Document Type: Article

References (5)

1. T. Takeshima et al., "A 3.3 V single-power-supply 64 Mb flash memory with dynamic bit-line latch (DBL) programming scheme," in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 148-149.
2. R. Womack et al., "A 16 Kb ferroelectric nonvolatile memory with a hit parallel architecture," in ISSCC Dig. Tech. Papers, Feb. 1989, pp. 242-243.
3. T. Sumi et al., "A 256 Kb nonvolatile ferroelectric memory at 3 V and 100 ns," in ISSCC Dig. Tech. Papers, Feb. 1994, pp. 268-269.
4. H. Koike et al., "A 60 ns 1 Mb nonvolatile ferroelectric memory with nondriven cell plate line write/read scheme," in ISSCC Dig. Tech. Papers, Feb. 1996 pp. 368-369.
5. 9 thin films," App. Phys. Lett., pp. 221-223, Jan. 1995.