A device level negative feedback in the emitter line of SCR-structures as a method to realize latch-up free ESD protection

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2003, Pages 105-111

  Concannon, A ^a   Vashchenko, V A ^a   Ter Beek, M ^a   Hopper, P ^a  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC LINES; ELECTRIC POTENTIAL; FEEDBACK; FLIP FLOP CIRCUITS;

HOLDING VOLTAGE;

THYRISTORS;

EID: 0037972885     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)

1. G. Groph, J. Bernier, "ESD protection for high frequency integrated circuits," Solid-State Electron., 1998; Vol. 38, pp. 1681-1689.
2. S. Dabral, T. J. Maloney, Basic ESD and I/O Design. New York: Wiley, 1998.
3. J. Z. Chen, A. Amerasekera, T. Vrotos, "Bipolar SCR ESD protection for high speed submicron Bipolar/BiCMOS frequency integrated circuits," in Proceedings of the IEDM, 1995, pp.337-340
4. S. L. Jang, S.H. Li, "MOSFET triggering silicon controlled rectifiers for electrostatic discharge protection circuits," Solid-State Electronics, 2001, Vol. 45, pp.1799-1803.
5. S. Voldman, N. Schmidt, R. Johnson, L. Lanzerotti, A. Joseph, C. Brennan, J. Dunn, D. Harame, "Electrostatic Discharge Characterization of Epitaxial-Base Silicon-Germanium Hetro Junction Bipolar Transistors" in Proceedings of ESD/EOS Symposium, 2000, pp. 239-250.
6. HBM MIL883-STD 3015.
7. IEC1000-4.2 specifications.
8. V. A. Vashchenko, Y. Martynov, V.F. Sinkevitch, "Electrical Instability and Filamentation in ggMOS protection structures," Solid-State Electronics, 1997, Vol.41, pp.1761-1767.
9. V. A. Vashchenko, et.al,. "Negative differential conductivity and isothermal drain breakdown of the GaAs MESFET," IEEE Trans. Electron Devices, 1996, Vol. 43, pp. 513-518.
10. J. Wu, P. Juliano, E. Rosenbaum, "Breakdown and latent damage of ultra-thin gate oxides under BSD stress conditions," in Proceedings of ESD/EOS Symposium, 2000, pp. 287-295.
11. T. Smedes, A. Heringa, J. van Zwol, and P.C de Jong, "The impact of Substrate Resistivity on ESD Protection Devices," in Proceedings of ESD/EOS Symposium, 2002, pp.354-361.
12. P. Salome, C. Leroux, D. Mariolle, D. Lafond, J.P. Chante, Crevel, G. Reimbold, "An attempt to explain thermally induced soft failures during low level ESD stresses: study of the differences between soft and hard NMOS failures," in Proceedings of ESD/EOS Symposium, 1997: 337-345.
13. V. A. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper "Comparison of ESD Protection Capability of lateral BJT, SCR and bi-directional SCR for Hi-Voltage BiCMOS Circuits", in Proceedings of Bipolar/ BiCMOS Circuits and Technology Meeting (BCTM), 2002, pp.181-184.
14. C. C. Russ, P.J. Mergens, K.G. Verhaege, J. Armer, P. C. Jozwiak, G. Kolluri, L. R. Avery, "GGSCR's: GGNMOS triggered silicon controlled rectifiers for ESD protection in deep sub-micron," in Proceedings of ESD/EOS Symposium, 2001; 22-31.
15. M. Ker, H. Chang, "Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup dange," Solid-State Electron., 2000, Vol.44, pp. 425-445
16. V. A. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper "Technology CAD Evaluation of BiCMOS Protection Structures Operation Including Spatial Thermal Runaway," in Proceedings of ESD/EOS Symposium, 2002, pp.101-110.
17. M. Mergens, C. Russ, K. Verhaege, J. Armer, P. Jozwiak, R. Mohn "High Holding Current SCRs (HHI-SCR) for ESD Protection and Latch-up Immune IC Operation," in Proceedings of ESD/EOS Symposium, 2002, pp. 11-17.
18. V. A. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper, "Increasing the ESD Protection Capability of Over-voltage NMOS Structures by Comb-Ballasting Region Design," Proceedings of International Reliability Physics Symposium 2003, (see paper 3D.7)
19. R.W. Dutton, A.J. Strojwas, "Perspectives on Technology and Technology-Driven CAD," IEEE Trans. on Comp. Aided Design of Int. Cir. and Sys., 2000. Vol. 19, pp. 1544-1560.
20. K. Esmark, W. Stadler, M. Wendel, H. Gobner, X. Guggenmos, W. Fichtner, "Advanced 2D/3D ESD Device Simulation - A powerful tool already used in a pre-Si Phase," in Proceeding of ESD/EOS Symposium, 2000, pp.420-429.
21. "TSUPREME4" "Two-Dimensional Process Simulation Program", "MEDICI, Versions 2002.2.0. "Two-Dimensional Device Simulation Program", Synopsys, 2002.
22. "TAURUS 3D PROCESS AND DEVICE", 2002.3.0, Synopsys, 2002