Increasing the ESD protection capability of over-voltage NMOS structures by comb-ballasting region design

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2003, Pages 261-268

  Vashchenko, V A ^a   Concannon, A ^a   Ter Beek, M ^a   Hopper, P ^a  

^a NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

Breakdown; Conductivity modulation; ESD Protection; Snapback; Triggering

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CONDUCTIVITY; ELECTRIC EQUIPMENT PROTECTION; MOS DEVICES; OVERVOLTAGE PROTECTION; SILICON;

CASCODED SNAPBACK;

ELECTRIC DISCHARGES;

EID: 0037972775     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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