Bridging fault modeling and simulation for deep submicron CMOS ICs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 8, 2002, Pages 941-953

  Favalli, Michèle ^a,b   Dalpasso, Marcello ^c  

^a IEEE   (Italy)

^b UNIVERSITY OF FERRARA   (Italy)

^c UNIVERSITY OF PADOVA   (Italy)

Author keywords

Bridging faults; Digital ICs testing; Fault simulation; Symbolic simulation

Indexed keywords

BRIDGING FAULTS;

ALGORITHMS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT TESTING; STATISTICAL METHODS;

CMOS INTEGRATED CIRCUITS;

EID: 0036683907     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.800457     Document Type: Article

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