Iddq testing for CMOS VLSI

Proceedings of the IEEE

Volumn 88, Issue 4, 2000, Pages 544-566

  Rajsuman, Rochit ^a  

^a Advantcsi Africa R and D Center   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; COST BENEFIT ANALYSIS; COST EFFECTIVENESS; DESIGN FOR TESTABILITY; ELECTRIC VARIABLES MEASUREMENT; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; RELIABILITY; SEMICONDUCTOR DEVICE TESTING; SENSORS; VLSI CIRCUITS;

CURRENT SENSOR; DEEP SUBMICRON TECHNOLOGY; DESIGN FOR TEST; FAULT DIAGNOSIS; QUIESCENT CURRENT MEASUREMENT; RELIABILITY TESTING; SYSTEM ON A CHIP TESTING; TEST EFFECTIVENESS;

INTEGRATED CIRCUIT TESTING;

EID: 0034171710     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.843000     Document Type: Article

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