-
1
-
-
0022722967
-
Fault and Error Models for VLSI
-
J.A. Abraham and W.K. Fuchs, "Fault and Error Models for VLSI," Proc. of the IEEE, Vol. 74, pp. 639-654, 1986.
-
(1986)
Proc. of the IEEE
, vol.74
, pp. 639-654
-
-
Abraham, J.A.1
Fuchs, W.K.2
-
2
-
-
0023210701
-
Realistic Fault Modeling for VLSI Testing
-
W. Maly, "Realistic Fault Modeling for VLSI Testing," Proc. of Design Automation Conf., 1987, pp. 173-180.
-
(1987)
Proc. of Design Automation Conf.
, pp. 173-180
-
-
Maly, W.1
-
3
-
-
0025481983
-
Testing for Parametric Faults in Static CMOS Circuits
-
F. Ferguson, M. Taylor, and T. Larrabee, "Testing for Parametric Faults in Static CMOS Circuits," Proc. of IEEE Int. Test Conf., 1990, pp. 436-443.
-
(1990)
Proc. of IEEE Int. Test Conf.
, pp. 436-443
-
-
Ferguson, F.1
Taylor, M.2
Larrabee, T.3
-
5
-
-
0017961684
-
Fault Modeling and Logic Simulation of CMOS and NMOS Integrated Circuits
-
R.L. Wadsack, "Fault Modeling and Logic Simulation of CMOS and NMOS Integrated Circuits," Bell Syst. Tech. J, Vol. 57, pp. 1449-1474, 1978.
-
(1978)
Bell Syst. Tech. J
, vol.57
, pp. 1449-1474
-
-
Wadsack, R.L.1
-
7
-
-
0026170365
-
Fault Simulation for General FCMOS ICs
-
M. Favalli, P. Olivo, F. Somenzi, and B. Riccò, "Fault Simulation for General FCMOS ICs," Jour. of Electronic Testing: Theory and Application, Vol. 2, pp. 181-190, 1991.
-
(1991)
Jour. of Electronic Testing: Theory and Application
, vol.2
, pp. 181-190
-
-
Favalli, M.1
Olivo, P.2
Somenzi, F.3
Riccò, B.4
-
9
-
-
0026153303
-
Fault Simulation of Unconventional Faults in CMOS ICs
-
M. Favalli, P. Olivo, M. Damiani, and B. Riccò, "Fault Simulation of Unconventional Faults in CMOS ICs," IEEE Transactions on CAD, Vol. 10, pp. 677-682, 1991.
-
(1991)
IEEE Transactions on CAD
, vol.10
, pp. 677-682
-
-
Favalli, M.1
Olivo, P.2
Damiani, M.3
Riccò, B.4
-
11
-
-
0027883887
-
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Logic Thresholds
-
P. Maxwell and R. Aitken, "Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Logic Thresholds," Proc. of IEEE Int. Test Conf., 1993, pp. 63-72.
-
(1993)
Proc. of IEEE Int. Test Conf.
, pp. 63-72
-
-
Maxwell, P.1
Aitken, R.2
-
12
-
-
0027833778
-
Fast and Accurate CMOS Bridging Fault Simulation
-
J. Rearick and J. Patel, "Fast and Accurate CMOS Bridging Fault Simulation," Proc. of IEEE Int. Test Conf., 1993, pp. 53-62.
-
(1993)
Proc. of IEEE Int. Test Conf.
, pp. 53-62
-
-
Rearick, J.1
Patel, J.2
-
13
-
-
0026944024
-
A Probabilistic Fault Model for 'Analog' Faults in Digital CMOS Circuits
-
M. Favalli, P. Olivo, and B. Riccò, "A Probabilistic Fault Model for 'Analog' Faults in Digital CMOS Circuits," IEEE Transaction on CAD, Vol. 11, pp. 1459-1462, 1992.
-
(1992)
IEEE Transaction on CAD
, vol.11
, pp. 1459-1462
-
-
Favalli, M.1
Olivo, P.2
Riccò, B.3
-
14
-
-
0022769976
-
Graph-Based Algorithms for Boolean Function Manipulation
-
R.E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Transactions on Computers, Vol. 35, pp. 677-691, 1986.
-
(1986)
IEEE Transactions on Computers
, vol.35
, pp. 677-691
-
-
Bryant, R.E.1
-
17
-
-
0002609165
-
A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran
-
F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran," Proc. of IEEE Int. Symp. on Circuit And Systems, 1985, pp. 663-698.
-
(1985)
Proc. of IEEE Int. Symp. on Circuit and Systems
, pp. 663-698
-
-
Brglez, F.1
Fujiwara, H.2
-
18
-
-
0022201294
-
Inductive Fault Analysis of MOS Integrated Circuits
-
Dec.
-
J. Shen, W. Maly, and F. Ferguson, "Inductive Fault Analysis of MOS Integrated Circuits," IEEE Design & Test of Computers, Vol. 2, pp. 33-26, Dec. 1985.
-
(1985)
IEEE Design & Test of Computers
, vol.2
, pp. 33-126
-
-
Shen, J.1
Maly, W.2
Ferguson, F.3
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