On the capability of delay tests to detect bridges and opens

Proceedings of the Asian Test Symposium

Volumn , Issue , 1997, Pages 314-318

  Chakravarty, Sreejit ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AT SPEED TESTING;

COMPUTATIONAL METHODS; COMPUTER SIMULATION; LOGIC GATES;

INTEGRATED CIRCUIT TESTING;

EID: 0031358007     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)

1. V. H. Champca, A. Rubio and J. Figueras, "Electrical Model of Floating Gate Defect in CMOS IC's: Implications on IDDQ Testing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 13, No. 3, pp. 359-369, 1994.
2. J. Chang and E. J. McCluskey, "Detecting Delay Flaws by Very-Low-Voltage Testing," Proceedings of IEEE Intemational Test Conference, pp. 367-376,1996.
3. E. B. Eichelberger, E. Lindbloom, J. A. Waicukauski and T. W. Williams, Structured Logic Testing, Prentice Hall, Englewood Cliffs, 1991.
4. H. Hao and E. J. McCluskey, "Resistive Shorts within CMOS Gates," Proceedings of IEEE International Test Conference, pp. 292-301, 1991.
5. C. F. Hawkins, J. M. Soden, A. W. Righter and F. J. Ferguson, "Defect Classes: An Overdue Paradigm for CMOS IC Testing," Proceedings of IEEE Intemational Test Conference, pp. 413-425, 1994.
6. C. L. Henderson, J. M. Soden and C. F. Hawkins, "The behaviour and testing implications of CMOS IC logic gate open circuits," Proceedings of IEEE Intemational Test Conference, pp. 302-310, October, 1991.
7. E. P. Hsieh, R. A. Rasmussen, L. J. Vidunas and W. T. Davis, "Delay Test Generation," Proceedings of ACMLEEE design Automation Conference, pp. 486-491,1977.
8. V. S. Iyengar, B. K. Rosen and I. Spillinger, "Delay Test Generation 2-Algebra and Algorithms," Proceedings of IEEE intemational Test Conference, pp. 867-876, September 1988.
9. S. Johnson, "Residual Charge on a Faulty Floating Gate MOS Transistor," Proceedings of IEEE Intemational Test Conference, pp. 555-561, 1994.
10. C. J. Lin and S. M. Reddy, "On Delay Fault Testing in Logic Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
11. W. Maly, "Realistic Fault Modeling for VLSI Testing," Proceedings of ACMAEEE Design Automation Conference, pp. 173-180, 1987.
12. W. Maly, "Modeling of lithography related yield losses for CAD for VLSI Circuits," IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-4, No. 4, pp. 166-177, 1985. 694-703,1987.
13. W. Maly, P. K. Nag and P. Nigh, "Testing oriented analysis of CMOS ICs with opens," Proceedings of ACMLEEE Intemational Conference on Computer-Aided Design, 1988, pp. 344-347.
14. P. Maxwell, R. Aitken, K. Kollitz and A. Brown, "IDDQan d AC Scan: The War Against Unmodelled Defects", Proceedings of IEEE Intemational Test Conference, pp. 250-258, 1996.
15. A. Pierzynska and S. Pilarski, "Non-Robust Versus Robust," Proceedings of IEEE Intemational Test Conference, pp. 123-131, 1995.
16. A. K. Pramanick and S. M. Reddy, "On the Detection of Delay Faults," Proceedings of IEEE Intemational Test Conference, pp. 845-856, September 1988.
17. A. K. Pramanick and S. M. Reddy, "On the Design of Path Delay Fault Testable Combinational Circuits," Proceedings of Intemational Fault Tolerant Computing Symposium, pp. 374-381, 1990.
18. M. Renovell and G. Cambon, "Electrical Analysis and Modeling of Floating-Gate Faults," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 11, No. 11, pp. 14.50-14.58, Nov. 1992.
19. J. A. Seguera, V. H. Champac, R. Rodrigues-Montanes, J. Figueras and A. Rubio, "Quiescent Current Analysis and Experimentation of Defective CMOS Circuits," pp. 51-62. Introduction to IDDQ Testing, Kluwer Academic Publishers. Eds: C. E Hawkins and R. Gulati.
20. G. L. Smith, "Model for Delay Faults Based upon Paths," Proceedings of IEEE Intemational Test Conference, pp. 342-349, 1985.
21. J. Van Sas, U. Swerts and M. Darquennes, "Towards an Effective IDDQ Test Vector Selection Strategy", Proceedings of IEEE lntemational Test Conference, pp.
22. H.T.Vierhaus, W.Meyer and U.Glaser, "CMOS bridges and resistive transistor fau1ts:Iddq versus delay effects," Proceedings of IEEE Intemational Test Conference, 1993, pp.83-91. 491-500, 1996.