Lazy transition systems and asynchronous circuit synthesis with relative timing assumptions

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 2, 2002, Pages 109-130

  Cortadella, Jordi ^a,b   Kishinevsky, Michael ^a,c   Burns, Steven M ^c   Kondratyev, Alex ^a,d   Lavagno, Luciano ^a,f   Stevens, Kenneth S ^a,c   Taubin, Alexander ^a,e   Yakovlev, Alexandre ^a,g  

^a IEEE   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^c INTEL CORPORATION   (United States)

^d CADENCE DESIGN SYSTEMS   (United States)

^e Theseus Logic   (United States)

^f POLITECNICO DI TORINO   (Italy)

^g NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

Asynchronous circuits; Lazy transition systems; Logic synthesis; Relative timing

Indexed keywords

ASYNCHRONOUS CIRCUITS; LAZY TRANSITION SYSTEMS; RELATIVE TIMING;

ALGORITHMS; COMPUTER AIDED DESIGN; CONSTRAINT THEORY; MATHEMATICAL MODELS; OPTIMIZATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036474587     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.980253     Document Type: Article

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