Synthesis of asynchronous control circuits with automatically generated relative timing assumptions

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 324-331

  Cortadella, Jordi ^a   Kishinevsky, Michael ^a   Burns, Steven M ^a   Stevens, Ken ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; DELAY CIRCUITS; LOGIC DESIGN; LOGIC GATES; MICROCOMPUTERS; OPTIMIZATION; PETRI NETS; TIMING CIRCUITS;

ASYNCHRONOUS CONTROL CIRCUITS; RELATIVE TIMING; REVOLVING ASYNCHRONOUS PENTIUM PROCESSOR INSTRUCTION DECODER;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 0033351703     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)