Efficient verification of timed automata using dense and discrete time semantics

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1703, Issue , 1999, Pages 125-141

  Bozga, Marius ^a   Maler, Oded ^a   Tripakis, Stavros ^a  

^a VERIMAG   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; AUTOMATA THEORY; CLOCKS; DESIGN; HARDWARE; RECONFIGURABLE HARDWARE; STATE SPACE METHODS;

ASYNCHRONOUS CHIPS; REPRESENTATION SCHEMES; STATE SPACE REPRESENTATION; SYMBOLIC TECHNIQUES; SYNCHRONOUS SYSTEM; TIMED AUTOMATA; VARIABLE-DIMENSION; VERIFICATION RESULTS;

SEMANTICS;

EID: 84878412319     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-48153-2_11     Document Type: Conference Paper

References (30)

1. R. Alur and D. L. Dill, A Theory of Timed Automata, Theoretical Computer Science 126, 183–235, 1994.
2. R. Alur and T. A. Henzinger, Logics and Models for Real-Time: A survey, J. W. de Bakker et al (Eds.), Real-Time: Theory in Practice, LNCS 600, 74-106, Springer, 1992.
3. R. Alur, and R. P. Kurshan, Timing Analysis in COSPAN, in R. Alur, T. A. Henzinger and E. Sontag (Eds.), Hybrid Systems III, LNCS 1066, 220-231, Springer, 1996.
4. E. Asarin, M. Bozga, A. Kerbrat, O. Maler, A. Pnueli and A. Rasse, Data- Structures for the Verification of Timed Automata, in O. Maler (Ed.), Proc. HART’97, LNCS 1201, 346-360, Springer, 1997.
5. E. Asarin, O. Maler and A. Pnueli, On the Discretization of Delays in Timed Automata and Digital Circuits, in R. de Simone and D. Sangiorgi (Eds), Proc. Concur’98, LNCS 1466, 470-484, Springer, 1998.
6. F. Balarin, Approximate Reachability Analysis of Timed Automata, Proc. RTSS’96, 52-61, IEEE, 1996.
7. M. Bozga, SMI: An Open Toolbox for Symbolic Protocol Verification, Technical Report 97-10, Verimag, 1997. http://www.imag.fr/VERIMAG/DISTSYS/SMI/.
8. W. Belluomini and C. J. Myers, Verification of Timed Systems Using POSETs, in A. J. Hu and M. Y. Vardi (Eds.), Proc. CAV’98, 403-415, LNCS 1427, Springer, 1997.
9. M. Bozga, O. Maler, A. Pnueli, S. Yovine, Some Progress in the Symbolic Verification of Timed Automata, in O. Grumberg (Ed.) Proc. CAV’97, 179-190, LNCS 1254, Springer, 1997.
10. J. A. Brzozowski and C-J. H. Seger, Asynchronous Circuits, Springer, 1994.
11. C. Daws, A. Olivero, S. Tripakis, and S. Yovine, The Tool KRONOS, in R. Alur, T. A. Henzinger and E. Sontag (Eds.), Hybrid Systems III, LNCS 1066, 208-219, Springer, 1996.
12. C. Daws and S. Tripakis, Model checking of Real-time Reachability Properties using Abstractions, Proc. TACAS’98, LNCS 1384, 1998.
13. C. Daws and S. Yovine, Reducing the Number of Clock Variables of Timed Automata, Proc. RTSS’96, 73-81, IEEE, 1996.
14. D. L. Dill, Timing Assumptions and Verification of Finite-State Concurrent Systems, in J. Sifakis (Ed.), Automatic Verification Methods for Finite State Systems, LNCS 407, 197-212, Springer, 1989.
15. J. C. Fernandez, A. Kerbrat, and L. Mounier, Symbolic Equivalence Checking, In C. Courcoubetis (Ed.), Proc. CAV’93, LNCS 697, Springer, 1993.
16. M. R. Greenstreet, STARI: SkewT olerant Communication, to appear in IEEE Transactions on Computers, 1997.
17. N. Halbwachs, Delay Analysis in Synchronous Programs, in C. Courcoubetis (Ed.), Proc. CAV’93, LNCS 697, 333-346, Springer, 1993.
18. T. Henzinger, Z. Manna, and A. Pnueli. What Good are Digital Clocks?, in W. Kuich (Ed.), Proc. ICALP’92, LNCS 623, 545-558, Springer, 1992. 129
19. K. Larsen, F. Larsson, P. Pettersson and W. Yi, Efficient Verification of Real-Time Systems: Compact Data Structure and State-Space Reduction, Proc. RTSS’98, 14-24, 1997.
20. K. G. Larsen, P. Pettersson and W. Yi, UPPAAL in a Nutshell, Software Tools for Technology Transfer 1/2, 1997.
21. H. R. Lewis, Finite-state Analysis of Asynchronous Circuits with Bounded Temporal Uncertainty, TR15-89, Harvard University, 1989.
22. O. Maler and A. Pnueli, Timing Analysis of Asynchronous Circuits using Timed Automata, in P. E. Camurati, H. Eveking (Eds.), Proc. CHARME’95, LNCS 987, 189-205, Springer, 1995.
23. F. Somenzi, CUDD: CU Decision Diagram Package, 1995.
24. J. Springintveld and F. W. Vaandrager, Minimizable Timed Automata, in B. Jonsson and J. Parrow(E ds.), Proc. FTRTFT’96, LNCS 1135, 130-147, Springer, 1996.
25. S. Tasiran, R. Alur, R. P. Kurshan and R. Brayton, Verifying Abstractions of Timed Systems, in Proc. CONCUR’96, 546-562, Springer, 1996.
26. S. Tasiran and R. K. Brayton, STARI: A Case Study in Compositional and Hierarchical Timing Verification, in O. Grumberg (Ed.) Proc. CAV’97, 191-201, LNCS 1254, Springer, 1997.
27. S. Tasiran, Y. Kukimoto and R. K. Brayton, Computing Delay with Coupling using Timed Automata, Proc. TAU’97, 1997.
28. R. J. van Glabbeek and W. P. Weijland, Branching-Time and Abstraction in Bisimulation Semantics (extended abstract), CS R8911, Centrum voor Wiskunde en Informatica, Amsterdam, 1989.
29. H. Wong-Toi and D. L. Dill, Approximations for Verifying Timing Properties, in T. Rus and C. Rattray (Eds.), Theories and Experiences for Real- Time System Development, World Scientific Publishing, 1994.
30. T. Yoneda and H. Ryu, Timed Trace Theoretic Verification Using Partial Order Reductions, in Proc. Async’99, 108-121, IEEE Press, 1999.