Verification of speed-dependences in single-rail handshake circuits

Proceedings - 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems

Volumn 1998-March, Issue , 1998, Pages 159-170

  Negulescu, Radu ^a   Peeters, Ad ^b  

^a UNIVERSITY OF WATERLOO   (Canada)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; CHAINS; DELAY CIRCUITS;

ANALOG SIMULATIONS; ASYNCHRONOUS CIRCUITS; DISCRETE STATE; HANDSHAKE CIRCUITS; ISOCHRONIC FORKS; SPEED DEPENDENCE; SPEED INDEPENDENT; TIMING ASSUMPTIONS;

TIMING CIRCUITS;

EID: 0344667936     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.1998.666502     Document Type: Conference Paper

References (21)

1. [vB92] K. van Berkel. Beware the isochronic fork. Integration, the VLSI journal, 13(2):103-128, June 1992.
2. [vB93] K. van Berkel. Handshake Circuits: An Asynchronous Architecture for VLSI Programming, vol ume 5 of International Series on Parallel Computation. Cambridge University Press, 1993.
3. [vBHP95] K. van Berkel, F. Huberts, A. Peeters. Stretching quasi delay insensitivity by means of extended isochronic forks. In Asynchronous Design Methodologies, pages 99-106. IEEE Computer Society Press, May 1995.
4. [BRB90] K. S. Brace, R. L. Rudell, R. E. Bryant. Efficient implementation of a BDD package. In Proceedings of the 27th ACM/IEEE Design Automation Conference, June 1990.
5. [BS95] J. A. Brzozowski and C.-J. H. Seger. Asynchronous Circuits. Springer-Verlag, 1995.
6. [Di89] D. L. Dill. Trace Theory for Automatic Hierarchical Verification of Speed-IndependentCircuits. ACM Distinguished Dissertations. MIT Press, 1989.
7. [Eb91] J. C. Ebergen. A formal approach to designing delay-insensitive circuits. Distributed Computing, 5(3):107-119, 1991.
8. [GC94] M. R. Greenstreet and P. Cahoon. How fast will the flip flop In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 77-86, 1994.
9. [Ho85] C. A. R. Hoare. Communicating Sequential Processes. Prentice-Hall, 1985.
10. [Jo92] M. B. Josephs. Receptive process theory. Acta Informatica, 29(1):17-31, 1992.
11. [KM91] R. Kurshan and K. McMillan. Analysis of digital circuits through symbolic reduction. IEEE Transactions on Computer-Aided Design, 10(11):1356-1371, 1991.
12. [KN94] M. Kuwako and T. Nanya. Timing-reliability evaluation of asynchronous circuits based on different delay models. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 22-31, November 1994.
13. [La92] L. Lavagno. Synthesis and Testing of Bounded Wire Delay Asynchronous Circuits from Signal Transition Graphs. PhD thesis, U.C. Berkeley, November 1992.
14. [Ma90] A. J. Martin. Programming in VLSI: From communicating processes to delay-insensitive circuits. In C. A. R. Hoare, editor, Developments in Concurrency and Communication, UT Year of Programming Series, pages 1-64. Addison-Wesley, 1990.
15. [MJCL97] C. E. Molnar, I. W. Jones, B. Coates, J. Lexau. A FIFO ring oscillator performance experiment. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, April 1997.
16. [My95] C. J. Myers. Computer-Aided Synthesis and Verification of Gate-Level Timed Circuits. PhD thesis, Dept. of Elec. Eng., Stanford University, October 1995.
17. [Ne95] R. Negulescu. Process spaces. Technical Report CS-95-48, Computer Science, University of Waterloo, December 1995. http://maveric.uwaterloo.ca/radu/ps.html
18. [Ne97] R. Negulescu. A technique for finding and verifying speed-dependences in gate circuits. In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Austin, Texas, December, 1997. A technical report version is available from, http://maveric.uwaterloo.ca/radu/ps.html
19. [Ne98] R. Negulescu. Event-driven verification of switchlevel correctness concerns. In International Conference on Application of Concurrency to System Design, Aizu-Wakamatsu, Japan, March 1998.
20. [Pe96] A. M. G. Peeters. Single-Rail Handshake Circuits. PhD thesis, Eindhoven Univ. of Technology, Eindhoven, The Netherlands, June 1996.
21. [Ve94] T. Verhoeff. A Theory of Delay-Insensitive Systems. PhD thesis, Eindhoven Univ. of Technology, Eindhoven, The Netherlands, May 1994.