Hazard-free implementation of speed-independent circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 9, 1998, Pages 749-771

  Kondratyev, Alex ^a,b,c   Kishinevsky, Michael ^a,b,c   Yakovlev, Alex ^a,b,c  

^a UNIVERSITY OF AIZU   (Japan)

^b INTEL CORPORATION   (United States)

^c NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

Asynchronous circuits; Gate level implementation, hazard freedom; Logic synthesis; Monotonous cover; Speed independence

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; FLIP FLOP CIRCUITS; LOGIC GATES;

SPEED-INDEPENDENT CIRCUITS;

COMPUTER AIDED LOGIC DESIGN;

EID: 0032167091     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.720313     Document Type: Article

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