Modeling and synthesis of timed asynchronous circuits

European Design Automation Conference - Proceedings

Volumn , Issue , 1994, Pages 460-465

  Vanbekbergen, Peter ^a   Goossens, Gert ^a   Lin, Bill ^a  

^a SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTATIONAL LINGUISTICS; CONSTRAINT THEORY; DELAY CIRCUITS; ELECTRIC NETWORK SYNTHESIS; GRAPHIC METHODS; RANDOM ACCESS STORAGE; SEMICONDUCTOR DEVICE MODELS; TIMING CIRCUITS;

ASYNCHRONOUS COMPILERS; SIGNAL TRANSITION GRAPH; TIMING CONSTRAINTS;

PROGRAM COMPILERS;

EID: 0028727996     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)