Formal verification of safety properties in timed circuits

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2000, Pages 2-11

  Peña, Marco A ^a   Cortadella, Jordi ^a   Kondratyev, Alex ^b   Pastor, Enric ^a  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b Theseus Logic   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT VERIFICATION; EVENT STRUCTURES; FORMAL VERIFICATIONS; LIMING CONSTRAINTS; NEW APPROACHES; REACHABILITY ANALYSIS; SAFETY PROPERTY; STATE SPACE; SYMBOLIC TECHNIQUES; TIMED CIRCUITS; TIMING ANALYSIS;

TIME MEASUREMENT;

EID: 77957931749     PISSN: 15228681     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2000.836774     Document Type: Conference Paper

References (27)

1. R. Alur and D. Dill. A Theory of Timed Automata. Theoretical Computer Science, 126:183-235, 1994.
2. R. Alur, A. Itai, R.P. Kurshan, and M. Yannakakis. Timing Verification by Successive Approximation. Information and Computation, 118(1):142-157, 1995.
3. T. Amon and H. Hulgaard. Symbolic time separation of events. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 83-93, April 1999.
4. A. Arnold. Finite Transition Systems. Prentice-Hall, 1994.
5. E. Asarin, M. Bozga, A. Kerbrat, O. Maler, A. Pnueli, and A. Rasse. Data structures for the verification of timed automata. In O. Maler, editor, Proc. HART'97, volume 1201 of LNCS, pages 346-360. Springer-Verlag, 1997. (Pubitemid 127044055)
6. F. Balarin and A.L. Sangiovanni-Vincentelli. An iterative approach to verification of real-time systems. Formal Methods in System Design, 6:67-95, January 1995.
7. W. Belluomini and C.J. Myers. Verification of timed systems using POSETs. In Proc. International Conference on Computer Aided Verification, pages 403-415, 1998.
8. M. Bozga, O. Maler, A. Pnueli, and S. Yovine. Some progress in the symbolic verification of timed automata. In O. Grumberg, editor, Computer-Aided Verification'97, volume 1254 of LNCS, pages 179-190. Springer-Verlag, 1997. (Pubitemid 127088975)
9. J. R. Burch. Delay models for verifying speed-dependent asynchronous circuits. In International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March 1992.
10. 20 states and beyond. In Proc. of the Fifth Annual Symposium on Logic in Computer Science, June 1990.
11. J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev. Lazy transition systems: application to timing optimization of asynchronous circuits. In Proc. ICCAD, November 1998.
12. O. Coudert, J. C. Madre, and C. Berthet. Verifying temporal properties of sequential machines without building their state diagrams. Computer-Aided Verification'90, pages 75-84, 1990.
13. S. Devadas, K. Keutzer, S. Malik, and A. Wang. Verification of asynchronous interface circuits with bounded wire delays. In Proc. ICCAD, pages 188-195, November 1992.
14. A. Gupta. Formal Hardware Verification Methods: A Survey. Formal Methods in System Design, 1:151-238, 1992.
15. T. Henzinger, Z. Manna, and A. Pnueli. Temporal proof methodologies for real-time systems. In Proc. of the I8th ACM Symposium on Principles of Programming Languages, pages 353-366, 1991.
16. H. Hulgaard and S. M. Burns. Bounded delay timing analysis of a class of CSP programs with choice. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 2-11, November 1994.
17. H. Kim and P.A. Beerel. Relative timing based verification of timed circuits and systems. In International Workshop on Logic Synthesis, June 1999.
18. O. Maler and A. Pnueli. Timing analysis of asynchronous circuits using timed automata. In P.E. Camurati and H. Eveking, editors, Proc. CHARME'95, volume 987 of LNCS, pages 189-205. Springer-Verlag, 1995.
19. A. Mazurkiewicz. Basic notions of trace theory. In J. W. Baker, W. P. de Roever, and G. Rozenberg, editors. Linear Time, Branching Time, and Partial Order in Logics and Models for Concurrency, volume 354 of LNCS, pages 285-363. Springer-Verlag, 1988.
20. K. L. McMillan and D. L. Dill. Algorithms for interface verification. In Proc. of the International Conference on Computer Design, October 1992.
21. R. Negulescu and A. Peeters. Verification of speed-dependences in single-rail handshake circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, March 1998.
22. M. Nielsen, G. Plotkin, and G. Winskel. Petri Nets, Event Structures and Domains. Theoretical Computer Science, 13:85-108, 1981.
23. M.A. Peña, J. Cortadella, A. Kondratyev, and E. Pastor. Formal verification of safety properties in timed circuits. Technical Report RR-99/49 http://www.ac.upc.es/homes/marcoa/TechReports.html, UPC/DAC, October 1999.
24. A. Semenov and A. Yakovlev. Verification of asynchronous circuits using time Petri-net unfolding. In Proc. Design Automation Conference, 1996.
25. R.E. Shostack. A practical decision procedure for arithmetic with function symbols. Journal of the ACM, 26(2): 351-360, April 1979.
26. K. Stevens, R. Ginosar, and S. Rotem. Relative timing. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 208-218, April 1999.
27. E. Verlin, G. de Jong, and B. Lin. Efficient partial enumeration for timing analysis of asynchronous systems. In Proc. Design Automation Conference, 1996.