Min-max timing analysis and an application to asynchronous circuits

Proceedings of the IEEE

Volumn 87, Issue 2, 1999, Pages 332-346

  Chakraborty, Supratik ^a,e   Dill, David L ^b,d   Yun, Kenneth Y ^c  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

^b Stanford University   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d STANFORD UNIVERSITY   (United States)

^e NATIONAL SCIENCE FOUNDATION   (United States)

Author keywords

3D circuits; Approximate timing Analysis; Asynchronous circuits; Extended burst mode circuits; Min max timing simulation; Polynomial time analysis; Reconvergent fanout analysis

Indexed keywords

ALGORITHMS; COMPUTER AIDED ANALYSIS; COMPUTER SIMULATION; LOGIC DESIGN; POLYNOMIALS;

FANOUT ANALYSIS; POLYNOMIAL ANALYSIS;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 0033079540     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.740025     Document Type: Article

References (42)

1. K. Y. Yun, Synthesis of Asynchronous controllers for heterogeneous systems," Ph.D. dissertation, Stanford Univ., Stanford, CA, 1994.
2. D. E. Muller And W. S. Bartky, A theory of Asynchronous circuits," Ami. Comput. Lab Harvard Univ., 1959, pp. 204-243.
3. W.a. Clark, Macromodular computer systems,"Proc. Spring Joint Computer Conf. (AFIPS), Apr.1967, vol. 30, pp. 335-336.
4. C. H. van Berkel And R. W. J. J. Saeijs, Compilation of communicating processes into delay-insensitive circuits,"Proc. Int. Conf. Computer Design: VLSI in Computers And Processors, Nov.1988, pp.157-162.
5. C. Berthet And E. Cerny, Synthesis of speed-independent circuits from Algebraic specifications,"Proc. Int. Symp. Circuits And Systems, 1988, vol. 2, pp.1869-1872.
6. E. Brunvand And R. F. Sproull, Translating concurrent programs into delay-insensitive circuits,"Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov.1989, pp. 262-265.
7. A. J. Martin, Programming in VLSI: From communicating processes to delay-insensitive VLSI circuits," Developments in Concurrency And Communications (UT Year of Programming Institute on Concurrent Programming Series), C.A.R. Hoare, Ed. Reading, MA: Addison-Wesley, 1990.
8. J. C. Ebergen, A formal Approach to designing delayinsensitive circuits," Distrib. Comput., vol. 5, No. 3, pp.107-119, 1991.
9. P. Beerel And T. H.-Y. Meng, Automatic gate-level synthesis of speed-independent circuits,"Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov.1992, pp. 581-586.
10. C. J. Myers And T. H.-Y. Meng, Synthesis of timed Asynchronous circuits,"IEEE Trans. VLSI Syst., vol.1, No. 2, pp.106-119, June 1993.
11. L. Lavagno, K. Keutzer, Anda. L. Sangiovanni-Vmcentelli, Synthesis of hazard-free Asynchronous circuits with bounded wire delays,"IEEE Trans. Computer-Aided Design, vol.14, pp. 61-86, Jan.1995.
12. VV. S. Coates, a. L. Davis, And K. S. Stevens, The post office experience: Designing A large Asynchronous chip,"Integr. VLSI J., vol.15, No. 3, pp. 341-366, 1993.
13. S. M. Nowick, Automatic synthesis of burst-mode Asynchronous controllers," Ph.D. dissertation, Stanford Univ., Stanford, CA, 1993.
14. W. K. C. Lam And R. K. Brayton, Timed Boolean Functions: A Unified Formalism for Exact Timing Analysis. Norwell, MA: Kluwer, 1994.
15. D.a. Huffman, The synthesis of sequential switching circuits," J. Franklin Inst., pp.161-190, 275-303, Mar./Apr.1954.
16. S. H. Unger, Asynchronous Sequential Switching Circuits. New York: Wiley, 1969.
17. M.a. Breuer Anda. D. Friedman, Diagnosis And Reliable Design of Digital Systems. Rockville, MD: Computer Science, 1976.
18. E. Ulrich, K. P. Lentz, S. Demba, And R. Razdan, Concurrent min-max simulation,"Proc. Europ. Conf. Design Automation, 1991, pp. 554-557.
19. T. M. McWilliams, Verification of timing constraints on large digital systems,"Proc. ACM/IEEE Design Automation Conf., 1980, pp.139-147.
20. K. Bowden, Design goals And implementation techniques for time-based digital simulation And hazard detection,"Proc. Int. Test Conf., 1982, pp.147-152.
21. N. Ishiura, Studies on logic simulation And hardware description languages," Ph.D. dissertation, Kyoto Univ., Kyoto, Japan, 1990.
22. D. Doukas Anda. S. LaPaugh, Clover: A timing constraints verification system,"Proc. ACM/IEEE Int. Workshop Timing Issues in the Specification And Synthesis of Digitial Systems, 1990.
23. A. R. Martello, Temporal Analysis for time bounded causal digital systems," Ph.D. dissertation, Univ. Pittsburgh, PA, 1993.
24. M. H. Linderman, Simulation of digital circuits in the presence of uncertainty," Ph.D. dissertation, Cornell Univ., Ithaca, NY, 1994.
25. S. Devadas, K. Keutzer, S. Malik, Anda. Wang, Verification of Asynchronous interface circuits with bounded wire delays," 1EEEJ. VLSI Signal Processing, vol. 7, pp.161-182, Feb.1994.
26. __, Event suppression: Improving the efficiency of timing simulation for synchronous digital circuits,"IEEE Trans. Computer-Aided Design, vol.13, pp. 814-822, June 1994.
27. N. Ishiura, M. Takahashi, And S. Yajima, Time symbolic simulation for Accurate timing verification of Asynchronous behavior of logic circuits,"Proc. ACM/IEEE Design Automation Conf., 1989, pp. 497-502.
28. N. Ishiura, Y. Deguchi, And S. Yajima, Coded time-symbolic simulation using shared binary decision diagram,"Proc. ACM/IEEE Design Automation Conf., 1990, pp.130-135.
29. E. B. Eichelberger, Hazard detection in combinational And sequential switching circuits,"IBM J. Res. Develop., vol. 9, No. 2, pp. 90-99, Mar.1965.
30. D. S. Kung, Hazard-nonincreasing gate-level optimization Algorithms,"Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov.1992, pp. 631-634.
31. T. J. Chakraborty, v. D. Agrawal, And M. L. Bushnell, Delay fault models And test generation for random logic sequential circuits,"Proc. ACM/IEEE Design Automation Conf., June 1992, pp.165-172.
32. S. Chakraborty And D. L. Dill, More Accurate polynomial-time min-max timing simulation,"Proc. 3rd Int. Symp. Advanced Research in Asynchronous Circuits And Systems, Apr.1997, pp.112-123.
33. T. Cormen, C. Leiserson, And R. Rivest, Introduction to Algorithms. New York: McGraw-Hill, 1990.
34. S. M. Nowick And D. L. Dill, Automatic synthesis of locallyclocked Asynchronous state machines,"Proc.1991 IEEE Int. Conf. Computer-Aided Design, Nov.1991, pp. 318-321.
35. P. Kudva, G. Gopalakrishnan, And H. Jacobson, A technique for synthesizing distributed burst-mode circuits,"Proc. ACM/IEEE Design Automation Conf., June 1996, pp. 67-70.
36. P. Kudva, Synthesis of Asynchronous systems targeting finite state machines," Ph.D. dissertation, Univ. Utah, Salt Lake City, 1995.
37. K. Y. Yun, D. L. Dill, And S. M. Nowick, Synthesis of 3D Asynchronous state machines,"Proc. IEEE Int. Conf. Computer Design: VLSI in Computers And Processors, Oct.1992, pp. 346-350.
38. K. Y. Yun And D. L. Dill, Automatic synthesis of 3D Asynchronous finite-state machines,"Proc.1992 IEEE/ACM Int. Conf. Computer-Aided Design, Nov.1992, pp. 576-580.
39. __, Unifying synchronous/asynchronous state machine synthesis,"Proc. IEEE/ACM Int. Conf. Computer-Aided Design, Nov.1993, pp. 255-260.
40. E. J. McCluskey, Logic Design Principles With Emphasis on Testable Semicustom Circuits. Englewood Cliffs, NJ: PrenticeHall, 1986.
41. "Hitachi High Speed CMOS Gate Array: HG62E Series Design Manual," Hitachi Co..
42. S. Chakraborty, D. L. Dill, K. Y. Yun, And K.-Y. Chang, Timing Analysis for extended burst-mode circuits,"Proc. 3rd Int. Symp. Advanced Research in Asynchronous Circuits And Systems, Apr.1997, pp.101-111.