Binning for IC quality: Experimental studies on the SEMATECH data

Proceedings - 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1998

Volumn 1998-December, Issue , 1998, Pages 4-10

  Singh, D ^a   Lakin, D R ^a   Nigh, P ^b  

^a AUBURN UNIVERSITY   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; DIES; FAULT TOLERANCE; INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS; TIMING CIRCUITS; VLSI CIRCUITS;

DEFECT CLUSTERING; DEFECT LEVELS; HIGH INCIDENCE; NEW APPROACHES; PRODUCTION TESTING; SEMATECH DATA; SEMICONDUCTOR MANUFACTURING; SUBMICRON CMOS;

DESIGN FOR TESTABILITY;

EID: 0007842872     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.1998.732145     Document Type: Conference Paper

References (10)

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3. A.D. Singh and C.M. Krishna, "On Optimizing VLSI Testing for Product Quality Using Die-Yield Prediction", IEEE Transactions on CAD, Vol 12, No 5, May 1993, pp. 695-709.
4. A.D. Singh and C.M. Krishna, "On the Eect of Defect Clustering on Test Transparency and IC Test Optimization", IEEE Transactions on Com-puters, Vol 45, No 6, June 1996, pp. 753-757.
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7. A.D. Singh, P. Nigh and C.M. Krishna, "Screening for Known Good Die Based on Defect Clustering: An Experimental Study", Proceedings 1997 Inter-national Test Conference, November 1997.
8. E.J. McCluskey, "IC Quality and Test Trans-parency", International Test Conference, 1990.
9. S.C. Seth and V.D. Agrawal, "Characterizing the LSI Yield Equation from Wafer Test Data", IEEE Transactions Computer-Aided Design, Vol CAD-3, 1984.
10. T.W. Williams and N.C. Brown, "Defect Level as a Function of Fault Coverage", IEEE Transactions on Computers, Vol C-30, 1981.