IC performance prediction for test cost reduction

1999 IEEE International Symposium on Semiconductor Manufacturing, ISSM 1999 - Conference Proceedings

Volumn , Issue , 1999, Pages 111-114

  Lee, Jungran ^a   Walker, D M H ^a   Milor, L ^b   Peng, Yeng ^b   Hill, G ^b  

^a TEXAS A AND M UNIVERSITY   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FORECASTING; INTEGRATED CIRCUITS; MANUFACTURE; SEMICONDUCTOR DEVICE MANUFACTURE; TIMING CIRCUITS; COSTS; INDUSTRIAL ELECTRONICS; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; SEMICONDUCTOR DEVICE MODELS; SILICON WAFERS;

AVERAGE NUMBERS; BUILDING MODEL; CIRCUIT PERFORMANCE; ELECTRICAL TESTS; PERFORMANCE PREDICTION; TEST COST REDUCTION;

COST REDUCTION; INTEGRATED CIRCUIT MANUFACTURE;

INTEGRATED CIRCUIT (IC) PERFORMANCE PREDICTION; WAFER ELECTRICAL TEST MEASUREMENT;

EID: 0033320941     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSM.1999.808750     Document Type: Conference Paper

References (8)

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