-
1
-
-
0030409504
-
IDDQ Test: Sensitivity Analysis of Scaling
-
Washington DC
-
Williams, T., et al, "IDDQ Test: Sensitivity Analysis of Scaling", International Test Conference, Washington DC, pp. 786-792, 1996
-
(1996)
International Test Conference
, pp. 786-792
-
-
Williams, T.1
-
3
-
-
85008014520
-
Deep Submicron CMOS Current IC Testing: Is There A Future?
-
Oct-Dec
-
Hawkins, C. F., and J. M. Soden, "Deep Submicron CMOS Current IC Testing: Is There A Future?", IEEE Design and Test of Computers, Oct-Dec. 1999, pp. 14-15.
-
(1999)
IEEE Design and Test of Computers
, pp. 14-15
-
-
Hawkins, C.F.1
Soden, J.M.2
-
4
-
-
0029487490
-
On the Effect of ISSQ Testing in Reducing Early Failure Rate
-
Wallquist, K., "On the Effect of ISSQ Testing in Reducing Early Failure Rate", Int'l Test Conf., 1995, pp. 910-914.
-
(1995)
Int'l Test Conf.
, pp. 910-914
-
-
Wallquist, K.1
-
5
-
-
0030409795
-
Burn-In Elimination of a High Volume Microprocessor Using IDDQ
-
Henry, T., and Soo, T., "Burn-In Elimination of a High Volume Microprocessor Using IDDQ", International Test Conference, 1996, pp. 242-249.
-
(1996)
International Test Conference
, pp. 242-249
-
-
Henry, T.1
Soo, T.2
-
6
-
-
0030397203
-
IDDQ and AC Scan: The War Against Unmodelled Faults
-
Washington, DC
-
Maxwell, P. C., et al, "IDDQ and AC Scan: The War Against Unmodelled Faults", International Test Conference, Washington, DC, 1996, pp. 250-258.
-
(1996)
International Test Conference
, pp. 250-258
-
-
Maxwell, P.C.1
-
7
-
-
0031361501
-
IDDQ Testing of a 180 MHz HP PA-RISC Microprocessor with Redundancy Programmed Caches
-
Washington, DC, Nov
-
Meneghini, T., and D. Josephson, "IDDQ Testing of a 180 MHz HP PA-RISC Microprocessor with Redundancy Programmed Caches", IEEE International Workshop on IDDQ Testing, Washington, DC, Nov. 1997, pp. 44-51.
-
(1997)
IEEE International Workshop on IDDQ Testing
, pp. 44-51
-
-
Meneghini, T.1
Josephson, D.2
-
8
-
-
0032313703
-
Failure Analysis of Timing and IDDQ-Only Failures from the SEMATECH Test Methods Experiment
-
Washington, DC, October
-
Nigh, P. et al, "Failure Analysis of Timing and IDDQ-Only Failures from the SEMATECH Test Methods Experiment", IEEE International Test Conference, Washington, DC, October 1998, pp. 43-52.
-
(1998)
IEEE International Test Conference
, pp. 43-52
-
-
Nigh, P.1
-
10
-
-
0031376341
-
Current Signatures: Application
-
Nov
-
Gattiker, A. E., and W. Maly, "Current Signatures: Application", Int. Test Conf., Nov. 1997, pp. 156-165.
-
(1997)
Int. Test Conf.
, pp. 156-165
-
-
Gattiker, A.E.1
Maly, W.2
-
11
-
-
84961964549
-
IDDQ Test and Diagnosis in Deep Submicron
-
Washington, DC
-
Sachdev, M., "IDDQ Test and Diagnosis in Deep Submicron", I IEEE International Workshop on IDDQ Testing, Washington, DC, pp. 84-89, 1995.
-
(1995)
IEEE International Workshop on IDDQ Testing
, pp. 84-89
-
-
Sachdev, M.1
-
12
-
-
0031382110
-
Intrinsic Leakage in Low Power Deep Submicron CMOS ICs
-
Nov
-
Keshavarzi, A., K. Roy, and C. F. Hawkins, "Intrinsic Leakage in Low Power Deep Submicron CMOS ICs", Proc. Int. Test Conf., Nov. 1997, pp. 146-155.
-
(1997)
Proc. Int. Test Conf.
, pp. 146-155
-
-
Keshavarzi, A.1
Roy, K.2
Hawkins, C.F.3
-
13
-
-
0030402140
-
Dynamic Characterization of Built-In Current Sensors Based on PN Junctions: Analysis and Experiments
-
December
-
Rius, J. and J. Figueras, "Dynamic Characterization of Built-In Current Sensors Based on PN Junctions: Analysis and Experiments", Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 9, No. 3, December, 1996, pp. 295-310.
-
(1996)
Journal of Electronic Testing: Theory and Applications (JETTA)
, vol.9
, Issue.3
, pp. 295-310
-
-
Rius, J.1
Figueras, J.2
-
14
-
-
84961912507
-
Experiments with an On-Chip IDDQ Current Sensor for VLSI Testing
-
Washington, DC
-
Singh, A. D., "Experiments with an On-Chip IDDQ Current Sensor for VLSI Testing", IEEE Int'l Workshop on IDDQ Testing, Washington, DC, 1995, pp. 45-49.
-
(1995)
IEEE Int'l Workshop on IDDQ Testing
, pp. 45-49
-
-
Singh, A.D.1
-
15
-
-
0031356194
-
ICCQ: A Test Method for Analog VLSI Based on Current Monitoring
-
Washington, DC, Nov
-
van Lammeren, J. P. M., "ICCQ: A Test Method for Analog VLSI Based on Current Monitoring", IEEE Int'l Workshop on IDDQ Testing, Washington, DC, Nov. 1997, pp. 24-28.
-
(1997)
IEEE Int'l Workshop on IDDQ Testing
, pp. 24-28
-
-
Van Lammeren, J.P.M.1
-
16
-
-
84961925701
-
-
U.S. Patent
-
W. Needham, et al, U.S. Patent 5,570,034, 1996.
-
(1996)
-
-
Needham, W.1
-
17
-
-
0033280471
-
Micro IDDQ Test Using Lorentz Force MOSFETs
-
K. Nose and T. Sakurai, "Micro IDDQ Test Using Lorentz Force MOSFETs", IEEE VLSI Technology Symp., 1999, pp. 167-168.
-
(1999)
IEEE VLSI Technology Symp.
, pp. 167-168
-
-
Nose, K.1
Sakurai, T.2
-
18
-
-
0031343645
-
IDDQ Characterization in Submicron CMOS
-
A. Ferre and J. Figueras, "IDDQ Characterization in Submicron CMOS", ITC97, pp. 136-145.
-
ITC97
, pp. 136-145
-
-
Ferre, A.1
Figueras, J.2
-
19
-
-
84886910586
-
Evaluation of Early Failure Screening Methods
-
October, Washington, DC
-
Barrette, T., et al, "Evaluation of Early Failure Screening Methods", IEEE International Workshop on IDDQ Testing, October, 1996, Washington, DC, pp. 14-27.
-
(1996)
IEEE International Workshop on IDDQ Testing
, pp. 14-27
-
-
Barrette, T.1
-
20
-
-
0030686636
-
An Experimental Study Comparing the Relative Effectiveness of Functional Scan, IDDQ and Delay-Fault Testing
-
Nigh, P., W. Needham, K. Butler, P. Maxwell, R. Aitken, "An Experimental Study Comparing the Relative Effectiveness of Functional Scan, IDDQ and Delay-Fault Testing", VLSI Test Symp. 1997, pp. 459-464.
-
(1997)
VLSI Test Symp
, pp. 459-464
-
-
Nigh, P.1
Needham, W.2
Butler, K.3
Maxwell, P.4
Aitken, R.5
-
21
-
-
0029700346
-
On Estimating Bounds of Quiescent Current for IDDQ Testing
-
Ferre, A. and J. Figueras, "On Estimating Bounds of Quiescent Current for IDDQ Testing", VLSI Test Symp. 1996, pp. 106-111.
-
(1996)
VLSI Test Symp
, pp. 106-111
-
-
Ferre, A.1
Figueras, J.2
-
22
-
-
0031351788
-
A Simulation-Based Method for Estimating Defect-Free IDDQ
-
Washington, DC, November
-
Maxwell, P. C., and J. R. Rearick, "A Simulation-Based Method for Estimating Defect-Free IDDQ", IEEE International Workshop on IDDQ Testing, Washington, DC, November, 1997, pp. 80-84.
-
(1997)
IEEE International Workshop on IDDQ Testing
, pp. 80-84
-
-
Maxwell, P.C.1
Rearick, J.R.2
-
23
-
-
0032306412
-
Estimation of Defect-Free IDDQ in Submicron Circuits Using Switch Level Simulation
-
Oct
-
Maxwell, P. and J. Rearick, "Estimation of Defect-Free IDDQ in Submicron Circuits Using Switch Level Simulation", ITC98, Oct. 1998, pp. 882-889.
-
(1998)
ITC98
, pp. 882-889
-
-
Maxwell, P.1
Rearick, J.2
-
24
-
-
0031361502
-
A Comprehensive Wafer Oriented Test Evaluation (WOTE) Scheme for the IDDQ Testing of Deep Sub-Micron Technologies
-
Washington, DC, Nov
-
A. D. Singh, "A Comprehensive Wafer Oriented Test Evaluation (WOTE) Scheme for the IDDQ Testing of Deep Sub-Micron Technologies", IEEE Int'l Workshop on IDDQ Testing, Washington, DC, Nov. 1997, pp. 40-43.
-
(1997)
IEEE Int'l Workshop on IDDQ Testing
, pp. 40-43
-
-
Singh, A.D.1
-
25
-
-
0032682919
-
On the Comparison of Δ IDDQ and IDDQ Testing
-
Dana Point
-
C. Thibeault, "On the Comparison of Δ IDDQ and IDDQ Testing", VTS99, Dana Point, pp. 143-150.
-
VTS99
, pp. 143-150
-
-
Thibeault, C.1
-
26
-
-
0033307906
-
An Histogram Based Procedure for Current Testing of Active Defects
-
C. Thibeault, "An Histogram Based Procedure for Current Testing of Active Defects", ITC99, pp. 714-723.
-
ITC99
, pp. 714-723
-
-
Thibeault, C.1
-
27
-
-
0033315396
-
IDDQ Testing in Deep Submicron Integrated Circuits
-
A. C. Miller, "IDDQ Testing in Deep Submicron Integrated Circuits", ITC99, pp. 724-729.
-
ITC99
, pp. 724-729
-
-
Miller, A.C.1
-
28
-
-
84961917369
-
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
-
P. C. Maxwell et al, "Current Ratios: A Self-Scaling Technique for Production IDDQ Testing", ITC98, pp. 882-889.
-
ITC98
, pp. 882-889
-
-
Maxwell, P.C.1
-
29
-
-
0033326421
-
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
-
P. Maxwell, et. al, "Current Ratios: A Self-Scaling Technique for Production IDDQ Testing", ITC99, pp. 738-748.
-
ITC99
, pp. 738-748
-
-
Maxwell, P.1
-
30
-
-
84961961204
-
Clustering Based Identification of Faulty ICs Using IDDQ Tests
-
S. Jandhyala et al, "Clustering Based Identification of Faulty ICs Using IDDQ Tests", IDDQ98, pp. 48-53.
-
IDDQ98
, pp. 48-53
-
-
Jandhyala, S.1
-
32
-
-
0033314416
-
Defect Detection Using Power Supply Transient Signal Analysis
-
A. Germida, Z. Yan, J. F. Plusquellic, F. Muradali, "Defect Detection Using Power Supply Transient Signal Analysis", ITC99, pp. 67-76.
-
ITC99
, pp. 67-76
-
-
Germida, A.1
Yan, Z.2
Plusquellic, J.F.3
Muradali, F.4
-
33
-
-
0033333871
-
Transient Current Testing of 0.25 μm CMOS Devices
-
B. Kruseman, P. Janssen, V. Zieren, "Transient Current Testing of 0.25 μm CMOS Devices", ITC99, pp. 47-56.
-
ITC99
, pp. 47-56
-
-
Kruseman, B.1
Janssen, P.2
Zieren, V.3
-
34
-
-
0033309299
-
Statistical Threshold Formulation for Dynamic IDD Test
-
W. Jiang, B. Vinnakota, "Statistical Threshold Formulation for Dynamic IDD Test", ITC99, pp. 57-66.
-
ITC99
, pp. 57-66
-
-
Jiang, W.1
Vinnakota, B.2
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