Effects of delay models on peak power estimation of VLSI sequential circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1997, Pages 45-51

  Hsiao, Michael S ^a   Rudnick, Elizabeth M ^a   Patel, Janak H ^a  

^a RUTGERS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ESTIMATION; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; SEQUENTIAL CIRCUITS;

DELAY MODELS; PEAK POWER ESTIMATION;

VLSI CIRCUITS;

EID: 0031374717     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.1997.643360     Document Type: Conference Paper

References (21)