Precomputation-Based Sequential Logic Optimization for Low Power

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 2, Issue 4, 1994, Pages 426-436

  Alidina, Mazhar ^a   Monteiro, Jose ^b   Devadas, Srinivas ^b   Ghosh, Abhijit ^c   Papaefthymiou, Marios ^d  

^a LUCENT TECHNOLOGIES   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^c MITSUBISHI ELECTRIC RESEARCH LABORATORIES   (United States)

^d YALE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK PARAMETERS; ELECTRIC NETWORK SYNTHESIS; ENERGY DISSIPATION; FORMAL LOGIC; LOGIC DESIGN; MINIMIZATION OF SWITCHING NETS;

LOW POWER CIRCUITS; PRECOMPUTATION;

SEQUENTIAL CIRCUITS;

EID: 0028727716     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.335011     Document Type: Article

References (13)

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